Telephonic communications – Line equalization or impedance matching
Reexamination Certificate
2001-04-16
2002-07-09
Chan, Wing F. (Department: 2643)
Telephonic communications
Line equalization or impedance matching
C379S394000, C379S039000
Reexamination Certificate
active
06418220
ABSTRACT:
FIELD OF THE INVENTION
The invention pertains to a network interface circuit. More particularly, the invention pertains to a network interface circuit which uses capacitive coupling for voltage isolation between a low voltage side and a line side of a telephone network and an extended feedback loop for impedance matching.
BACKGROUND OF THE INVENTION
Telephone network interface circuits, i.e., data access arrangements (DAAs), for international applications require high voltage isolation and compliance with various country-specific parameters. The technical specifications for network interfaces include, among other things, (1) voltage isolation specifications between the low voltage side (the customer equipment side) and the network, (2) specific on-hook impedance requirements, (3) balancing of the line, referred to as impedance matching, (4) time delay requirements with respect to signals, and (5) absence of data on certain prescribed signalling frequencies.
High voltage isolation is necessary because customer equipment can place hazardously high voltages and currents on telephone lines which can damage central office equipment or even injure personnel. Further, data signal amplitudes must be maintained below certain maximum levels in order to avoid overloading the network and causing excessive cross-talk. On-hook impedance requirements also are specified because the central office must evaluate line conditions based on the difference between on-hook and off-hook impedance and also because the on-hook impedance must be sufficiently large so that the central office can drive the telephone ringer without requiring excessive power. Impedance matching is needed to control hum, cross-talk, and signal reflection at interfaces. Finally, time delay specifications and reserved signalling frequencies are established for billing protection for local telephone operating companies. These technical specifications and others for network connections vary widely from country to country.
For economic reasons, among others, it is desirable to design telephone network equipment that can, with minor adaptations, be used to meet the specifications of different countries.
FIG. 1
depicts a prior art circuit
100
for interfacing end user terminal equipment to a telephone network. The load impedance Z
L
represents the specific impedance parameters of the telephone network. High voltage isolated switches
101
,
102
, and
103
are connected across the interface and are programmed in combination with a transmission impedance Z
S
to provide the required impedance match to Z
L
. One disadvantage of circuit
100
in connection with use in international markets is the need for a parallel array of a large number of high voltage isolated switches to generate a reasonable image match, i.e., impedance matching, between a user side and a line side of the network, to meet the different specifications of various countries, such as return loss requirements. These high voltage isolated switches are expensive, and, if present in sufficient numbers, will make a network interface circuit too large and costly to be practical where cost, size and programmability are paramount concerns. Accordingly, there is a need for a simplified network interface that eliminates the large number of high voltage isolated switches required for programming the network's specific parameters in accordance with the prior art as depicted in FIG.
1
.
FIG. 2
illustrates another prior art circuit
200
which is intended to produce an output impedance Z
O
to match a line side impedance Z
N
of a network. Circuit
200
includes a transmit path having an operational amplifier circuit A
201
, and a feedback path that includes an operational amplifier circuit A
202
and an emulation impedance Z
EM
. The operational amplifier circuit A
201
provides a gain for a voltage signal applied from signal source
210
. Using standard circuit analysis techniques, Z
O
of circuit
200
is defined as:
Z
O
=
(
R
205
+
Z
EM
)
R
SENSE
(
K
+
1
)
R
205
+
Z
EM
,
Where
K
=
(
1
+
R
201
R
202
)
(
R
204
R
203
)
A proper selection of Z
EM
in circuit
200
is intended to set Z
O
to match the impedance Z
N
. However, as one skilled in the art will realize from equation 1, Z
EM
is not easily separable from the other scaling terms, i.e., the other circuit elements, such as resistors, which scale Z
EM
. More specifically, Z
O
cannot be isolated into an impedance term and a separately distinguishable scale term. As such, circuit
200
suffers the disadvantage of having poor control of the output impedance Z
O
because Z
EM
cannot be effectively scaled in a practical manner. Thus, while circuit
200
is intended to provide an impedance match to Z
N
, this objective is frustrated by the difficulty in scaling Z
EM
to set Z
O
. Moreover, circuit
200
also suffers the disadvantage of not having voltage isolation between the line side and the low voltage side to protect against hazardous voltages and currents. Accordingly, circuit
200
does not provide a practical solution for impedance emulation across a high voltage boundary.
Although other efforts have been made to address impedance emulation in a network interface context using amplifier based circuits, these efforts have not been successful for several reasons. Among these reasons is that the prior art circuit topologies have not solved the noise problems associated with frequency related amplifier effects.
Accordingly, it is an object of the present invention to provide a simplified and less costly network interface that provides both impedance matching and voltage isolation between the line side and low voltage side of a network without using expensive high voltage isolation switches and the like.
It is another object of the present invention to provide a network interface circuit that utilizes capacitive coupling across the high voltage isolation boundary.
It is a further object of the present invention to provide a network interface circuit in which the CODEC is provided on the line side of the high voltage isolation interface.
It is yet a further object of the present invention to provide a network interface circuit in which impedance matching is provided by an extended feedback loop comprised of digital filter circuits.
SUMMARY OF THE INVENTION
In accordance with the present invention, a high voltage isolation network interface circuit is provided in which the CODEC is positioned on the line side of the high voltage isolation interface. The coding and decoding is performed by means of &Sgr;/&Dgr; analog-to-digital conversion and digital-to-analog conversion. In this manner, the high voltage interface can be provided by differentially driven capacitors. Further, the differential driver and differential receiver on the line side of the capacitors are digital as are all filters on the low voltage side of the capacitive interface.
The use of digital filters to provide the necessary transfer functions for setting the various AC and DC country-specific parameters allows for a wider range of operation and easier adaptation to meet various specifications since the transfer functions of the digital filters can be controlled and altered by reprogramming the filter coefficients.
Several advantages flow from the positioning of the &Sgr;/&Dgr; converters on the line side of the interface rather than on the low voltage side. First, only three interface line pairs are needed since the &Sgr;/&Dgr; data stream is one bit wide. One differential line pair is needed in the transmit direction to carry data. One differential line pair is used in the receive direction to carry data. The clock signal can be included with the data on this differential pair or, alternately, may be carried on a separate path. In the latter situation, there would be a third pair of differential capacitors and related circuitry. Accordingly, the number of high voltage interfaces is minimized. Further, by using &Sgr;/&Dgr; modulated signals across the capacitive voltage boundary, the data is essentially modulated at the ov
Fischer Jonathan Herman
Hollenbach Keith Eugene
Laturell Donald Raymond
Witmer Steven Brooke
Agere Systems Guardian Corp.
Chan Wing F.
Synnestvedt & Lechner LLP
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