Extended errors correcting device having single package error co

Details Extended errors correcting device having single package error co Extended errors correcting device having single package error co

1988-11-28

1990-10-02

Atkinson, Charles E.

Excavating

371 381, 371 401, G06F 1110

Patent

active

049611933

ABSTRACT:
An apparatus and method for correcting data words from a memory is provided in which coded data is divided into a plurality of multi-bit packages of b bits each. The coded data comprises n-bit words with r error correcting code bits and n-r data bits. The invention is capable of correcting one package which has suffered at least one hard failure and a single soft error located in a different package. The invention involves the use of an error correcting code which gives a first syndrome when the data word has suffered a first error coming from at least one error in a first package and a single error in a different second package, which also gives a second syndrome when the data word has suffered a second error coming from at least one error in the above first package, and a single error in a third package. The error correcting code is such that equality of the first and second syndromes results in the equality of the first and second errors.

REFERENCES:
patent: 4464753 (1984-08-01), Chen
patent: 4661955 (1987-04-01), Arlington et al.
patent: 4862463 (1989-08-01), Chen
Aichelmann, Jr., Fault-Tolerant Design Techniques for Semiconductor Memory Applications, IBM J. Res. Develop., vol. 28, No. 2, Mar. 1984, pp. 177-183.
Reddy, A Class of Linear Codes for Error Control in Byte-per-Card Organized Digital Systems, IEEE, 1978, pp. 455-459.
Chen, SEC-DED Codes with Package Error Detection Capability, IBM Tech. Discl. Bulletin, vol. 22, No. 6, Nov. 1979, pp. 2356-2359.

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