Fishing – trapping – and vermin destroying
Patent
1995-06-07
1996-03-26
Chaudhari, Chandra
Fishing, trapping, and vermin destroying
437 7, 437149, H01L 21265
Patent
active
055019943
ABSTRACT:
An integrated circuit containing high voltage PMOS and/or NMOS devices as well as low voltage PMOS and/or NMOS devices and a simple low cost method for making same that is adaptable to many types of semiconductor processes; furthermore, the breakdown voltage of the high voltage devices is easily adjusted so that the value of R.sub.on can be optimized. High voltage MOS devices 6 and 7 are formed on substrate 10 using essentially the same process steps as are used to form low voltage MOS devices 8 and 9. Low values of R.sub.on are obtained by selecting impurity concentration levels for HV drift region n-tank 21 and for HV drift region p-tank 41 so that the depletion region distance D1 bounded by equipotential lines 301a and 301j and the depletion region distance D1a bounded by equipotential lines 401a and 401h are smaller than the physical size D2 and D2a of drift regions 41 and 21, respectively.
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Chaudhari Chandra
Holland Robby
Kesterson James C.
Laws Gerald E.
Texas Instruments Incorporated
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