Extended chip select reset apparatus and method

Details Extended chip select reset apparatus and method Extended chip select reset apparatus and method

1995-07-20

1997-10-07

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327299, 327160, 377107, H03K 1722

Patent

active

056752717

ABSTRACT:
An extended chip select reset circuit to generate a reset signal for a device, such as a SLAC, using the chip select line. When the chip select line has been maintained in an active state for at least a predetermined amount of time corresponding to a plurality of data clocks, then a reset signal is generated in order to reset the device. The plurality of data clocks is more than a number of data clocks used to clock in a word of data to the device in a normal mode of operation.

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K. Nishimura et al., "Advanced Analog Subscriber Line Interface Circuit LSI" NEC Research and Devolpment, vol. 32, No. 4, Oct. 1991.

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