Boots – shoes – and leggings
Patent
1983-03-31
1987-04-14
Chan, Eddie P.
Boots, shoes, and leggings
G06F 1300
Patent
active
046583505
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to storage addressing and, more particularly, to apparatus and method for controlling access to the same or different pages of storage by a plurality of direct storage (memory) access (DMA) channels.
2. Discussion of the Prior Art
This invention is an improvement on that of U.S. patent application Ser. No. 231,653, now U.S. Pat. No. 4,443,847 filed Feb. 5, 1981 for PAGE ADDRESSING MECHANISM by D. J. Bradley et al, and on that of U.S. patent application Ser. No. 231,639, now U.S. Pat. No. 4,374,417 filed Feb. 5, 1981 for METHOD FOR USING PAGE ADDRESSING MECHANISM by D. J. Bradley et al, both of common assignee. Since the filing of the present application, patents have been granted for the foregoing Bradley et al. patent applications: U.S. Pat. No. 4,443,847 for application Ser. No. 231,653 and U.S. Pat. No. 4,374,417 for the application Ser. No. 231,639.
The Bradley references extend the size of memory which can be addressed by an address bus carrying N bits of information from the normal 2.sup.N locations to a multiple of 2.sup.N by providing a plurality of register means each of which is separately programmable to store data capable of being selectably provided as page signals. Selection of the page registers is made by control signals manifesting the then occurring storage operation, such as instruction fetch, storage read, or storage write operations. However, the Bradley addressing technique suffers in a system where there exists a plurality of direct storage (or memory) access channels (DMA). All DMA channels which can operate simultaneously must be directed to the same extended region of the storage address space. This may result in the necessity for double buffering of data, which reduces system performance and increases storage requirements.
SUMMARY OF THE INVENTION
In accordance with a preferred embodiment of this invention, there is provided an improvement in a computing system storage addressing apparatus which extends the addressing capability of an address bus to enable direct storage (memory) access (DMA) channels to operate simultaneously in either the same storage page or different storage pages. Accordingly, there is provided in a computing system including a processor, a plurality of storage devices, a data bus and an address bus interconnecting said processor and said storage devices, and a DMA device controlling connection of a plurality of DMA channels to the address bus and data bus, a plurality of address register means for storing page address signals loaded from the processor, and gating means for gating to the address bus page address signals from the address register means corresponding to a currently active DMA channel.
BRIEF DESCRIPTION OF THE DRAWINGS
One preferred embodiment of this invention is hereinafter described with reference being made to the following drawings in which:
FIG. 1 is a block diagram showing a typical DMA apparatus for addressing DMA channels to system storage.
FIG. 2 is a block diagram showing the apparatus of the invention for addressing a plurality of DMA channels into the same or distinct regions of system storage;
FIGS. 3A and 3B are block diagrams showing the bus and addressing apparatus of FIG. 2 in greater detail; these are aligned as shown in FIG. 3; and
FIG. 4 is a map diagram of storage address space illustrating DMA page rollover.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Herein, by way of example, processor unit 10 comprises an Intel 8088 microprocessor with a twenty bit address bus 12 capable of addressing in excess of one million locations in storage 16, and an 8 bit data bus 14. Storage 16 may comprise standard read only storage and random access memory devices.
Input/output devices 18 are coupled to data bus 14 for transferring data with respect to storage 16 under control of DMA controller 20. DMA controller 20 herein comprises an Intel 8237 or Intel DMA 8257 device with a capacity for coupling four channels (one is illustrated) to the eight bit data bus
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Eggebrecht Lewis C.
Kummer David A.
Beckstrand Shelley M.
Chan Eddie P.
International Business Machines Corp.
Lieber Robert
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