Boots – shoes – and leggings
Patent
1994-04-06
1996-08-20
Trans, Vincent N.
Boots, shoes, and leggings
364488, G06F 1750
Patent
active
055485243
ABSTRACT:
A method for generating hierarchical netlists for gate level or transistor level circuits having instances with properties defined by algebraic expressions. The present invention avoids duplication of instance definitions using a method of expression promotion in a computer aided design system capable of simple parameter passing, whereby expressions are replaced by tokens in the netlist, and moved up the hierarchy to a level where they can be fully evaluated. The present invention also provides a specific embodiment for implementing the expression promotion method used for netlisting.
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Coultas Robyn D.
Hernandez Celimo P.
Cadence Design Systems Inc.
Trans Vincent N.
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