Patent
1974-08-23
1976-12-21
Adams, Jr., Russell E.
354 50, 354 51, 354 60A, G03B 708
Patent
active
039991911
ABSTRACT:
An electronic camera shutter control circuit having a reversible counter for counting a number of pulses proportional to the duration of an exposure time. When the camera shutter is opened pulses are subtracted from the memory content of the reversible counter until the counter content is zero and the exposure is terminated. The reversible counter includes a final stage which does not change state if the number of pulses applied to the counter exceeds the memory capacity of the counter. For this condition the exposure time is first controlled by the charging time of a capacitor until a voltage stored in the capacitor exceeds a certain value whereupon the memory content of the counter is subtracted until it is zero and the exposure is terminated.
REFERENCES:
patent: 3748979 (1973-07-01), Wada
patent: 3824608 (1974-07-01), Toyoda
patent: 3827065 (1974-07-01), Wada
patent: 3836262 (1974-09-01), Yata et al.
patent: 3843265 (1974-10-01), Egli et al.
Saito Takeo
Seki Youichi
Adams Bruce L.
Adams, Jr. Russell E.
Burns Robert E.
Lobato Emmanuel J.
Seiko Koki Kabushiki Kaisha
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