Exposure of desired node in a multi-layer integrated circuit usi

Details Exposure of desired node in a multi-layer integrated circuit usi Exposure of desired node in a multi-layer integrated circuit usi

1998-09-04

2000-05-30

Bowers, Charles

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

438700, 438737, H01L 21302

Patent

active

060690798

ABSTRACT:
Aspects for exposing local areas for desired nodes in a multi-layer integrated circuit are described. In an exemplary method aspect, the method includes exposing at least one desired local area using focused ion beam etching, and performing reactive ion etching to complete delayering of the at least one desired local area to gain access to at least one lower level node of the integrated circuit. The exposing step further includes using a high current ion beam in the focused ion beam etching.

REFERENCES:
patent: 5616921 (1997-04-01), Talbot et al.
patent: 5825035 (1998-10-01), Mizumura et al.
Wolf and Tauber, Silicon Processing for the VLSI Era vol. 1--Process Technology, 1986, Lattice Press, pp. 510-511 and Chapter 16.

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