Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – With structure for mounting semiconductor chip to lead frame
Reexamination Certificate
2002-09-09
2004-11-16
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
With structure for mounting semiconductor chip to lead frame
C257S787000, C257S692000, C257S670000, C257S668000
Reexamination Certificate
active
06818973
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
(Not Applicable)
STATEMENT RE: FEDERALLY SPONSORED RESEARCH/DEVELOPMENT
(Not Applicable)
BACKGROUND OF THE INVENTION
The present invention relates generally to integrated circuit chip package technology, and more particularly to a QFP exposed pad package having exposed leads on the bottom of the package body thereof, and a method of creating such exposed leads in a cost-effective manner.
Integrated circuit dies are conventionally enclosed in plastic packages that provide protection from hostile environments and enable electrical interconnection between the integrated circuit die and an underlying substrate such as a printed circuit board (PCB). The elements of such a package include a metal leadframe, an integrated circuit die, bonding material to attach the integrated circuit die to the leadframe, bond wires which electrically connect pads on the integrated circuit die to individual leads of the leadframe, and a hard plastic encapsulant material which covers the other components and forms the exterior of the package.
The leadframe is the central supporting structure of such a package. A portion of the leadframe is internal to the package, i.e., completely surrounded by the plastic encapsulant. Portions of the leads of the leadframe extend externally from the package or are partially exposed within the encapsulant material for use in electrically connecting the package to another component. In certain semiconductor packages, a portion of the die pad of the leadframe also remains exposed within the exterior of the package for use as a heat sink.
One type of semiconductor package commonly known in the electronics field is referred to as a quad flat pack (QFP) package. A typical QFP package comprises a thin, generally square package body defining four peripheral sides of substantially equal length. Protruding from each of the four peripheral sides of the package body are a plurality of leads which each have a generally gull-wing configuration. Portions of the leads are internal to the package body, and are electrically connected to respective ones of the pads or terminals of a semiconductor die also encapsulated within the package body. The semiconductor die is itself mounted to a die pad of the QFP package leadframe. In certain types of QFP packages referred to as QFP exposed pad packages, one surface of the die pad is exposed within the bottom surface of the package body.
There is a current need in the electronics industry for a QFP exposed pad package which includes leads which are exposed within the bottom surface of the package body and are included as an addition to those protruding from the sides of the package body. The present invention provides such a QPF exposed pad package wherein leads exposed within the bottom surface of the package body are provided through the use of standard, low-cost leadframe design techniques. The exposed leads of the present invention are created through utilizing a standard leadframe with additional lead features that are isolated subsequent to a mold process through the use of a partial saw method. These, as well as other features and attributes of the present invention, will be discussed in more detail below.
BRIEF SUMMARY OF THE INVENTION
In accordance with the present invention, there is provided a method of cost-effectively creating high frequency electrical signal I/O paths on the bottom of a quad flat pack (QFP) package without features that would otherwise degrade electrical performance, and the QFP package itself fabricated as a result of the implementation of such methodology. These objectives are satisfied in the present invention through the creation of electrically isolated, exposed leads on the bottom of a QFP package, and more particularly a QFP exposed pad package. More particularly, the exposed leads of the present invention are created through the utilization of a standard leadframe with additional lead features that are isolated subsequent to a mold process through the use of a partial saw method. In this regard, after a certain point in the manufacturing process (i.e., after mold and plating), the exposed leads are electrically isolated from other structures in the leadframe through the completion of a partial saw cut into the molded bottom surface of the package body of the QFP package.
One of the primary benefits of the QFP package of the present invention is that it provides additional I/O or power/ground with very low parasitic inductance due to extremely short wire lengths. This enables very high frequency I/O structures which standard QFP packages are not capable of providing. In addition to the exposed leads being electrically isolated from other standard leads in the QFP package of the present invention, such exposed leads are also formed to be as short as possible. Though an exposed lead could be created by down-setting the lead finger part of a typical lead, such a fabrication technique creates a long antenna structure that seriously degrades electrical performance. By using the above-described partial saw process, this “excess” lead portion can be removed, and the antenna effect removed from the circuit.
In the present invention, the exposed lead structure of the QFP package is connected to other structures in the leadframe to enable processing during manufacturing. In one embodiment, the exposed leads are connected to the die pad of the leadframe to maintain structural integrity during the manufacturing process. The exposed leads of the leadframe are downset with the die pad so they are exposed within the bottom surface of the package body of the QFP package during the package body molding process. After mold and plating, the exposed leads are isolated by partial sawing as indicated above. In another embodiment of the present invention, the exposed leads are connected to other leads or lead fingers of the leadframe to maintain structural integrity during the manufacturing process. Again, the exposed leads are downset so as to be exposed within the bottom surface of the package body of the QFP package during the molding process for the package body. After mold and plating, the exposed leads are again isolated through the implementation of the partial sawing process.
In yet another embodiment, the exposed leads are connected to a ring that may be used for ground connection to the die pad, with the ring being attached to the tie bars of the leadframe. The exposed leads are connected to the ring to maintain structural integrity during the manufacturing process, and are downset so as to be exposed within the bottom surface of the package body of the QFP package during the package body molding process. After mold and plating, the exposed leads are isolated through the implementation of the partial sawing process. In a still further embodiment of the present invention, the exposed leads are connected to the die pad through the use of a connecting bar to hold the exposed leads in place, with the exposed leads further being inset into prescribed areas within the die pad. The exposed leads are downset so as to be exposed within the bottom surface of the package body of the QFP package during the molding process for the package body, with the exposed leads being isolated through the implementation of the partial sawing process after mold and plating. The present invention finds particular utility in relation to QFP packages due to the specific need of low inductance signal pads for these typically large packages, but may also be applied to any gull-wing leaded semiconductor package.
The present invention is best understood by reference to the following detailed description when read in conjunction with the accompanying drawings.
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Amkor Technology Inc.
Flynn Nathan J.
Greene Pershelle
Stetina Brunda Garred & Brucker
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