Exposed die leadless plastic chip carrier

Details Exposed die leadless plastic chip carrier Exposed die leadless plastic chip carrier

1999-12-03

2001-09-25

Powell, William A. (Department: 1765)

Etching a substrate: processes

Forming or treating electrical conductor article

Forming or treating lead frame or beam lead

C216S020000, C257S678000, C257S690000, C438S106000, C438S745000, C438S754000

Reexamination Certificate

active

06294100

ABSTRACT:

FIELD OF THE INVENTION
This invention relates in general to integrated circuit packaging, and more specifically to an improved process for fabricating a leadless plastic chip carrier which does not require a die attach pad.
BACKGROUND OF THE INVENTION
According to well known prior art IC (integrated circuit) packaging methodologies, semiconductor dice are singulated and mounted using epoxy or other conventional means onto respective die pads (attach paddles) of a leadframe strip. Traditional QFP (Quad Flat Pack) packages incorporate inner leads which function as lands for wire bonding the semiconductor die bond pads. These inner leads typically require mold locking features to ensure proper positioning of the leadframe strip during subsequent molding to encapsulate the package. The inner leads terminate in outer leads that are bent down to contact a mother board, thereby limiting the packaging density of such prior art devices.
In order to overcome these and other disadvantages of the prior art, the Applicants previously developed a Leadless Plastic Chip Carrier (LPCC). According to Applicants' LPCC methodology, a leadframe strip is provided for supporting up to several hundred devices. Singulated IC dice are placed on the strip die attach pads using conventional die mount and epoxy techniques. After curing of the epoxy, the dice are gold wire bonded to peripheral internal leads. The leadframe strip is then molded in plastic or resin using a modified mold wherein the bottom cavity is a flat plate. In the resulting molded package, the die pad and leadframe inner leads are exposed. By exposing the bottom of the die attach pad, mold delamination at the bottom of the die paddle is eliminated, thereby increasing the moisture sensitivity performance. Also, thermal performance of the IC package is improved by providing a direct thermal path from the exposed die attach pad to the motherboard. By exposing the leadframe inner leads, the requirement for mold locking features is eliminated and no external lead standoff is necessary, thereby increasing device density and reducing package thickness over prior art methodologies. The exposed inner leadframe leads function as solder pads for motherboard assembly such that less gold wire bonding is required as compared to prior art methodologies, thereby improving electrical performance in terms of board level parasitics and enhancing package design flexibility over prior art packages (i.e. custom trim tools and form tools are not required). These and several other advantages of Applicants' own prior art LPCC process are discussed in Applicants' co-pending patent application Ser. No. 09/095,803, the contents of which are incorporated herein by reference.
Applicants' LPCC production methodology utilizes saw singulation to isolate the perimeter I/O row as well as multi-row partial lead isolation. Specifically, the leadframe strip is mounted to a wafer saw ring using adhesive tape and saw-singulated using a conventional wafer saw. The singulation is guided by a pattern formed by fiducial marks on the bottom side of the leadframe strip. Also, special mold processing techniques are used to prevent the mold flow from bleeding onto the functional pad area and inhibiting electrical contact. Specifically, the exposed die pad surface is required to be deflashed after molding to remove any molding compound residue and thereby allow the exposed leads and die attach pad to serve as solder pads for attachment to the motherboard.
According to subsequently filed U.S. patent application Ser. No. 09/288,352, an etch back process is provided for the improved manufacture of Applicants' LPCC IC package. The leadframe strip is first subjected to a partial etch on one or both of the top and bottom surfaces in order to create a pattern of contact leads (pads) and a die attach pad (paddle). After wire bonding the contacts to a singulated semiconductor die, followed by overmolding and curing of the mold, the leadframe strip is exposed to a second full etch immersion for exposing the contact pads in an array pattern (i.e. multi-row) or perimeter pattern (i.e. single row), as well as the die attach pad. In the case of a package with multi-row I/O leads, this etch back step eliminates the requirement for two additional saw singulation operations (i.e. to sever the inner leads from the outer leads), and in both the single-row and multi-row configurations, the etch back step eliminates post mold processing steps (e.g. mold deflashing) and ensures superior device yield over the processing technique set forth in Applicants' prior application No. 09/095,803. Additionally, using this technique allows for higher I/O pad density and also allows for pad standoff from the package bottom which reduces stress in the solder joint during PCB temp cycling.
SUMMARY OF THE INVENTION
According to the present invention, an Exposed Die Leadless Plastic Chip Carrier (EDLPCC) is fabricated utilizing an improved method, whereby no die attach pad is required, in contrast with Applicants' prior LPCC fabrication processes. This results in a low package profile, extremely small IC package assembly, availability of corner areas of the package for additional input/output (I/O), and optional soldering of the exposed die to a circuit mother board for enhanced thermal performance.
Packages with no die pad are known in the prior art. However, such prior art IC packages use non-conductive epoxy applied to the inner leads of the package in order to attach the semiconductor die. This process contributes to the height of the package, increases signal inductance, and increases fabrication costs over other prior art IC packages. Because such devices are a form of SOIC-type package (Small Out Line Integrated Circuit) with leads that project downwardly out of the package into feet (i.e. not a pad array package), there is no exposed die. The die must be placed on top of the leads, which have mold compound under them, and the leads stick out of the side of the package and then bend downwardly. Such devices also offer much lower I/O density than the EDLPCC of the present invention.


REFERENCES:
patent: 4530152 (1985-07-01), Roche et al.
patent: 4685998 (1987-08-01), Quinn et al.
patent: 5976912 (1999-11-01), Fukutomi et al.
patent: 6001671 (1999-12-01), Fjelstad
patent: 59-208756 (1984-11-01), None

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