Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2000-12-07
2003-05-20
Lebentritt, Michael S. (Department: 2824)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S127000, C257S701000, C257S778000, C257S787000
Reexamination Certificate
active
06566164
ABSTRACT:
BACKGROUND
1. Technical Field
This invention is related to the packaging of semiconductor dies in general and, in particular, to a method and apparatus for connecting the die of a high power semiconductor device to an associated substrate with a metal strap that is exposed through a protective body of material encapsulating the entire assembly, thus providing for low electrical resistance and high thermal dissipation.
2. Related Art
FIGS. 1 and 2
are top plan and side elevation views, respectively, of a prior art embodiment of an 8-lead standard outline integrated circuit (“SOIC-8”) lead frame-type of power MOSFET semiconductor device
10
that has a conductive metal strap
12
electrically connecting a semiconductor die
14
to a metal portion
16
B of a lead-frame-type substrate
16
.
In the exemplary prior art MOSFET device
10
of
FIGS. 1 and 2
, the drain terminals of one or more individual MOSFETs (not visualized) formed in the die
14
are electrically connected to a metal or polysilicon first conductive layer
23
located on a downwardly-oriented first surface of the die. First conductive layer
23
of is, in turn, electrically connected to the metal die paddle
20
of a first portion
16
A of the lead frame
16
by, e.g., a layer
22
of solder or an electrically conductive adhesive. The die paddle
20
is integrally connected to each of four leads (
5
-
8
) of the first portion
16
A in this embodiment.
The source terminals of the one or more individual MOSFETs in the die
14
are connected to a metal or polysilicon second conductive layer
24
(
FIG. 2
) on an opposing upwardly oriented second surface of the die. The second conductive layer
24
on the die
14
is electrically connected to a second portion
16
B of substrate
16
through an electrically conductive layer
36
, metal strap
12
, and electrically conductive layer
38
. Second portion
16
B includes leads
1
-
3
in this embodiment.
The strap
12
comprises a planar cover portion
30
at an inner first end thereof, a planar flange portion
34
at an opposite outer second end thereof, and an oblique connection portion
32
between cover portion
30
and flange portion
34
. Cover portion
30
includes a first surface
30
a that is electrically connected to the second conductive layer
24
by electrically conductive layer
36
, and an opposite second surface
30
b
that faces toward the top of the package when oriented as shown in FIG.
2
. Second surface
30
b
and all other portions of strap
12
are covered by encapsulant
18
. The flange portion
34
of the strap
12
connects to the second portion
16
B of the substrate
16
by a lap joint using an electrically conductive layer
38
.
The metal strap
12
is made of a conductive metal, typically copper or a copper alloy. As illustrated in
FIG. 2
, with the device
10
oriented as shown, the first surface
30
a
of the cover
30
and bottom surface of flange
34
portions of the strap
12
lap over the top surfaces of the die
14
and the second portion
16
B of the substrate
16
, respectively, and are respectively joined thereto with layers
36
,
38
of, e.g., solder or an electrically conductive epoxy.
The gate terminals of the individual MOSFETs are connected to a third conductive layer, or gate pad
26
, located on the upper second surface of the die
14
(i.e., the same surface of die
14
as second conductive layer
24
). The gate pad
26
, which is electrically isolated from the second conductive layer
24
, is electrically connected to a third portion
16
C of substrate
16
by a bond wire
28
(see FIG.
1
). Third portion
16
C includes a lead
4
, and is electrically isolated from, but coplanar with, first and second portions
16
A and
16
B of substrate
16
.
Encapsulant
18
fully encloses die
14
and metal strap
12
, and encloses a portion of the lead frame substrate
16
, leaving the ends of leads
1
-
8
exposed for connection to other circuit components. Encapsulant
18
is typically molded plastic.
Pertinent dimensions of device
10
include: an area of die
14
that is 2 by 2 to 8 by 8 mm×mm; a height of die
14
that is 0.2 to 0.3 mm; a height of cover portion
30
that is 0.1 to 0.2 mm; and a thickness of encapsulant
18
above second surface
30
b
that is 0.1 to 0.3 mm. The width of strap
12
is primarily a function of the area of die
14
and second conductive layer
24
. The length of strap
12
is a function of the area of die
14
and second conductive layer
24
and the closeness of paddle
20
to second portion
16
B of substrate
16
.
Metal strap
12
of device
10
provides for improved thermal dissipation characteristics and lower electrical resistance in comparison to earlier configurations in which bond wires were used rather than metal strap
12
. Despite the improvements offered by the use of metal strap
12
, however, a need exists for a method and apparatus that provides an even greater degree of heat dissipation.
SUMMARY OF THE INVENTION
The present invention provides methods and apparatuses for packaging a semiconductor die. Among other features, the packages provide increased heat dissipation capabilities compared to prior art designs.
In one embodiment of a semiconductor device within the present invention, a high power semiconductor die is electrically connected to a substrate on which the die is mounted, e.g., a lead frame, with a metal strap. The die, substrate, and metal strap are encapsulated by an insulative, protective body in such a way that a portion of the metal strap is exposed to the outside environment. The exposed surface allows for increased thermal dissipation and less heat buildup during operation of the device.
An exemplary method for making such a package includes the provision of a semiconductor die, an interconnective substrate, and a conductive metal strap. After the die, substrate, and metal strap are electrically interconnected, an insulative encapsulant is provided (e.g., by molding) over the die and portions of the substrate and strap in a manner that leaves an upper surface of the strap above the die exposed to the environment. In other embodiments, recesses may be formed in the exposed surface of the strap to further increase heat dissipation. In a further alternative embodiment, heat-radiating metal protrusions may be formed on, or fastened, to the exposed surface of the metal strap.
The present invention is also applicable to other types of semiconductor devices. In one embodiment, a first surface of a metal strap is thermally connected, but not electrically connected, to an active surface of a memory, logic, or microprocessor die within rows of edge bond pads formed on the active surface of the die. An opposite surface of the strap is exposed to ambient through the encapsulant, which results in improved thermal dissipation.
These and other aspects of the present invention may be better understood in view of the accompanying drawings and the following detailed description.
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patent
Gillett Blake A.
Glenn Thomas P.
Amkor Technology Inc.
Bever Hoffman & Harms LLP
Lebentritt Michael S.
Luu Pho M.
Parsons James E.
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