Amplifiers – With semiconductor amplifying device – Including differential amplifier
Reexamination Certificate
2001-12-14
2003-11-18
Mottola, Steven J. (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including differential amplifier
C330S256000
Reexamination Certificate
active
06650182
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to amplifiers, and more particularly relates to a nonlinear transconductance amplifier for improving a response time of the amplifier to widely varying load conditions.
BACKGROUND OF THE INVENTION
In certain applications employing an amplifier, the load conditions experienced by the amplifier can often change significantly and abruptly. Conventional amplifiers experiencing widely varying load conditions typically utilize a large compensation capacitor coupled to the output of the amplifier in order to stabilize the amplifier over a wide range of output loads that may be encountered. Due to the size of the compensation capacitor that is required, however, the response time of the amplifier is significantly reduced. One such application in which load conditions can change rapidly is in a hard disk drive preamplifier system, which generally requires a low loop bandwidth for undistorted data recovery and fast settling time to meet write-to-read mode transition specifications.
Present hard disk drive system specifications require fast mode changes, for example, from a write mode to a read mode on the order of about 200 nanoseconds (ns) or less. In the read mode, the bias loop time constant should be greater than 100 microseconds (&mgr;s). In the write mode, large write signals may couple through read and write heads and through interconnects between the heads and the disk drive preamplifier. The coupled write mode signal amplitude can be much higher than the read mode signal. Thus, the parasitic coupling between write and read signal paths drives the read path direct current (dc) bias points far from their normal quiescent operating points during the write mode. Consequently, when the preamplifier transitions from write to read mode, the read bias loop sees a large error signal.
To simultaneously meet fast write-to-read mode transition requirements while providing low loop bandwidth during the read mode, a timing circuit
104
has been used in conjunction with an operational amplifier
102
, as is shown in FIG.
1
. In this manner, the transconductance of the amplifier
102
in the bias loop is increased by switching a large current to the amplifier for a predetermined period when changing from write mode to read mode. In U.S. Pat. No. 5,940,235 to Sasaki et al., a reproducing circuit for a magnetic head uses exponential current amplification without employing timing circuitry. Some of the drawbacks to this circuit arrangement, however, include difficulty in controlling the slope of the output current and a threshold range of the amplifier, as well as providing a very narrow threshold range. The threshold range is the region in which the output current is essentially zero (or very small) for an input differential voltage that is close to zero. Outside this threshold range, the transconductance (i.e., output-current-to-input-voltage ratio) relation is an exponential function. If the threshold range is narrow, the read mode bias loop will be undesirably affected by a normal read signal and the amplifier will possess a loop bandwidth that is too large.
U.S. Pat. No. 6,181,203 to Newlin discloses a nonlinear transconductance amplifier which has an output transfer characteristic that exhibits two different nonlinear relationships depending on the input differential signal level applied to the amplifier. The amplifier requires a dual differential pair of input bipolar devices and a corresponding bipolar current mirror for each of the four input devices. Consequently, the amplifier requires substantial area on a silicon wafer and dissipates a significant amount of quiescent current. A pair of emitter degeneration resistors in two of the four current mirrors, in conjunction with a pair of emitter degeneration resistors associated with the dual differential input devices, provide control over the knee point at which the two nonlinear relationships switch. However, due at least in part to the number of resistive elements affecting this knee point, accurately setting the knee point of the amplifier can be quite difficult to accomplish. Moreover, this circuit configuration may be susceptible to temperature and process variations.
Accordingly, there exists a need for an amplifier circuit having an improved response time to widely varying load conditions, without employing timing circuitry. Moreover, it would be desirable to provide an amplifier having reduced quiescent current dissipation and improved stability over temperature and process variations.
SUMMARY OF THE INVENTION
The present invention provides an improved amplifier which simultaneously meets fast write-to-read mode transition requirements while possessing a low loop bandwidth for undistorted data recovery. Furthermore, the amplifier of the present invention accomplishes these advantages without employing timing circuitry and the necessary overhead and/or noise often associated with such circuitry. The amplifier exhibits a transconductance that is substantially zero or linear when an input differential voltage presented to the amplifier is zero or small and a transconductance that is large or nonlinear for comparatively large input signals. A threshold region where the output of the amplifier is substantially zero can be easily set and tightly controlled by adjusting a single circuit element.
In accordance with one aspect of the invention, an exponential transconductance amplifier includes a linear differential input stage and a nonlinear transconductance stage operatively coupled to the differential input stage. The differential input stage includes first and second inputs forming a non-inverting input and an inverting input, respectively, of the amplifier for receiving an input differential signal. The nonlinear transconductance stage generates an output of the amplifier that exhibits a linear transconductance which is substantially zero or linear when the input differential signal is within a predetermined range and exhibits a large nonlinear transconductance when the input differential signal is outside the predetermined range. In accordance with another aspect of the invention, the nonlinear transconductance amplifier includes temperature compensation circuitry for providing a threshold region that is substantially constant over a predetermined temperature range of operation.
REFERENCES:
patent: 5008632 (1991-04-01), Sutterlin
patent: 5940235 (1999-08-01), Sasaki et al.
patent: 6181203 (2001-01-01), Newlin
1. P.E. Allen et al., “CMOS Analog Circuit Design,” 7.4 Comparator with Hysteresis, copyright by Saunders College Publishing, a division of Holt, Rinehart and Winston, Inc., pp. 349-357, 1987.
Kim Jong K.
Nainar Elangovan
Straub Michael P.
Agere Systems Inc.
Ryan & Mason & Lewis, LLP
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