Boots – shoes – and leggings
Patent
1992-09-08
1995-09-05
Teska, Kevin J.
Boots, shoes, and leggings
364488, 364578, G06F 1750
Patent
active
054484979
ABSTRACT:
A methodology for the redesign of sequential VLSI circuits to increase the circuit speed involves cascading the circuit over a plurality of time frames without the memory elements, identifying any long false paths in the cascaded circuit, reconfiguring the original circuit to eliminate the false paths while providing fanout to preserve functionality, and retiming the reconfigured circuit to reduce circuit delay.
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patent: 5278769 (1994-01-01), Bair et al.
patent: 5365528 (1994-11-01), Agrawal et al.
Charles E. Leiserson, "Optimizing Synchronous Circuitry by Retiming" published in Advanced Research in VLSI: Proceedings of the Third Caltech Conference, pp. 23-36, Computer Science Press, 1983.
Sharad Malik, "Performance Optiming of Pipelined Circuits" published in Proceedings of the Int'l Conference on Computer-Aided Design, Nov. 1990 pp. 410-413.
Sharad Malik, "Retiming and Resynthesis: Optimizing Sequential Networks with Combinational Techniques", published in IEEE Transactions on Computer-Aided Design, vol. CAD-10 No. 1, pp. 74-84 Jan. 1991.
Ashar Pranav
Dey Sujit
Malik Sharad
NEC Research Institute Inc.
Teska Kevin J.
Torsiglieri Arthur J.
Wieland Susan
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