Expansion bus system for replicating an internal bus as an exter

Details Expansion bus system for replicating an internal bus as an exter Expansion bus system for replicating an internal bus as an exter

1994-07-26

1996-10-01

Pan, Daniel H.

Boots, shoes, and leggings

364DIG1, 364DIG2, 395309, 395307, G06F 946, G06F 1324, G06F 13364

Patent

active

055617727

ABSTRACT:
A compressed I/O bus system for a general-purpose computer multiplexes 32 bit data and addresses on 32 of 42 dedicated parallel signal paths, and optimizes the bus structure by mapping bus requests made by peripheral devices to "high" memory portions of system RAM not dedicated to other purposes. In one aspect a bus controller is programmable to select translation routines stored in system RAM, allowing various models and types of CPUs to be supported. In this aspect, supported CPUs are interchangeable in the system. In another aspect a default interface attaches to the compressed I/O bus of the invention, and translates bus states between the optimized compressed bus and one of an ISA bus or an EISA bus.

REFERENCES:
patent: 5125093 (1992-06-01), McFarland
patent: 5163156 (1992-11-01), Leung et al.
patent: 5170470 (1992-12-01), Pindar et al.
patent: 5261107 (1993-11-01), Klim et al.
patent: 5261114 (1993-11-01), Raasch et al.

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