Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1998-12-07
2002-04-23
Metjahic, Safet (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S760020, C324S765010
Reexamination Certificate
active
06377061
ABSTRACT:
This invention relates generally to the field of integrated circuit packages and more specifically to apparatus and methods for testing fine lead pitch semiconductor packages.
BACKGROUND OF THE INVENTION
The lead count of surface mount semiconductor devices has been increasing for many years, driven by the need for more power and signal input/output. At the same time, there has been a strong push for smaller outline of the device packages, motivated by the requirement to conserve board space in assembly. These trends are conflicting and have resulted in ever smaller pitch of the package leads. Narrower and closely spaced leads, in turn, make mechanical handling more difficult due to weakened strength and tighter proximity; they also result in distortions of electrical testing due to electrical losses and stray effects.
Known technology for the electrical testing of surface mount semiconductor devices leaves much to be desired. Most test contactors currently available for high lead count devices utilize hinged lids, attached lid devices or latches, or are mechanically actuated by mechanisms to move and engage the contacts. The extra hardware of such contactors is difficult to adapt to an automated test environment. In most applications, this limits the process to high-cost and time consuming manual test operation. In addition, the excessive contact length of most conventional contactors and their long spring-loaded contact pins introduce a high inductance path and electrical noise into the test environment. Furthermore, they make the contacts mechanically fragile. Contact manipulation with lead combs or extra alignment features in conventional contactors create electrical test problems when used with high speed semiconductor devices and are subject to excessive mechanical failure and poor device alignment. Through-hole or soldered pin methods for installation in conventional test contactors are especially cumbersome.
SUMMARY OF THE INVENTION
The invention provides improved apparatus and methods for testing fine lead pitch semiconductor packages. It has particular application to semiconductor surface mount packages, especially to multi-layer ceramic chip carriers of the quad flat pack type with ceramic tie bars. The invention enables an effective expansion of lead pitch for testing and the provision of test contactors exploiting this opportunity for easier as well as more precise testing.
It is an object of the present invention to extend the concept of automated testing to fine lead pitch semiconductor surface mount packages.
Another object of the present invention is to provide a testing method with high alignment flexibility and contact reliability while retaining lead coplanarity and avoiding stress or damage to the delicate leads.
Another object of the present invention is to provide a method for electrically truthful testing even at high frequencies, with significantly reduced test noise.
Another object of the present invention is to provide a testing method applicable to various semiconductor device families for military and commercial applications, independent of package thermal expansion properties.
Another object of the present invention is to provide a method of expanding the effective lead pitch of high lead count semiconductor packages for reliable testing.
These objects have been achieved by producing periodically staggered arrays of electrically conductive vias in low-cost ceramic tie bars needed to support fine pitch leads, and using them in a test apparatus featuring mirror-imaged staggered arrays of electrically conductive bores embedded in insulating material. These combinations have been suscessfully employed for automated testing of high frequency semiconductor devices.
In one embodiment of the invention, the fine pitch leads of a chip carrier are supported by tie bars made of electrically insulating material, which include conductive vias arranged in a periodically staggered array. At one surface, each via contacts one lead of the package, while at an opposite surface the via is adapted to be contacted by a metal pin provided in a test contactor. The pattern of the staggering of the vias is designed so that the contacting pins are spatially separated for electrical testing, resulting in an effective lead pitch for testing expanded two-to-flour fold compared to the actual physical lead pitch.
In another embodiment of the invention, test apparatus is provided that utilizes a low profile contact base ready to receive the device-to-be-tested. The contact base comprises electrically insulating material featuring an array of bores, each one containing an subassembly of a metallic pin activated by an elastic and electrically conductive support. The subassembly is non-selective for electrical frequency in electrical tests. The array of bores mirrors the array of conductive vias in the ceramic tie bars of the chip carrier-to-be-tested. The contact base, in turn, is positioned in a housing of electrically insulating material which consists of a base for connecting to the tester and a lid with notches, into which hinges attached to the base are clamped.
The technical advances represented by the invention, as well as the objects thereof, will become apparent from the following description of a preferred embodiment of the invention when considered in conjunction with the accompanying drawings, and the novel features set forth in the appended claims.
REFERENCES:
patent: 3810016 (1974-05-01), Chayka et al.
patent: 4962356 (1990-10-01), Eberlein et al.
patent: 5086269 (1992-02-01), Nobi
patent: 5176525 (1993-01-01), Nierescher et al.
patent: 5245277 (1993-09-01), Nguyen
patent: 5247248 (1993-09-01), Fukunaga
patent: 5517125 (1996-05-01), Posedel et al.
patent: 5572144 (1996-11-01), Davidson et al.
patent: 5610437 (1997-03-01), Frechette
patent: 5914529 (1999-06-01), King et al.
patent: 6006424 (1999-12-01), Kim et al.
patent: 0902473 (1999-03-01), None
Noble, Jr. Don E.
Settle Kirk F.
Hollington Jermele M.
Honeycutt Gary C.
Metjahic Safet
Navarro Arthur I.
Telecky Fred
LandOfFree
Expanded lead pitch for semiconductor package and method of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Expanded lead pitch for semiconductor package and method of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Expanded lead pitch for semiconductor package and method of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2900095