Expandable memory for the suppression of phase jitter in a telec

Details Expandable memory for the suppression of phase jitter in a telec Expandable memory for the suppression of phase jitter in a telec

1977-12-21

1979-04-03

Claffy, Kathleen H.

Telegraphy

Systems

Printing

179 15BA, 179 15BS, 178 691, H04J 306

Patent

active

041478959

ABSTRACT:
Binary message signals arriving over a PCM link at a retransmitting station, with a predetermined average bit cadence subject to random variations, are cyclically written in an 8-stage buffer register under the control of an 8-pulse writing counter stepped by clock pulses extracted from the incoming bit stream. The contents of the buffer register are read out under the control of an 8-pulse reading counter stepped by a local pulse generator whose pulse rate substantially corresponds to the predetermined cadence. Any deviations of the actual bit rate from the predetermined cadence are detected in a phase comparator receiving mutually interleaved monitoring pulses, once per 8-bit cycle, from the two counters. The comparator comprises a flip-flop whose alternate setting and resetting by the two pulse trains produces a square wave of 50% duty ratio when the counters are in step; otherwise, the detected mean amplitude of the square wave adjusts the operating frequency of a quartz-controlled oscillator, forming part of the local pulse generator, to compensate for the deviation.

REFERENCES:
patent: 3504126 (1970-03-01), Inose et al.
patent: 3597552 (1971-08-01), Goto
patent: 3805180 (1974-04-01), Widmer
patent: 3992581 (1976-11-01), Davis
patent: 4025720 (1977-05-01), Pachynski, Jr.
patent: 4058683 (1977-11-01), Fenoglio
patent: 4075428 (1978-02-01), Ghisler et al.

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