Execution unit and method for using architectural and working re

Details Execution unit and method for using architectural and working re Execution unit and method for using architectural and working re

1997-06-30

1999-10-12

An, Meng-Ai T.

Electrical computers and digital processing systems: processing

Processing architecture

Superscalar

712 32, 712214, 712215, G06F 938

Patent

active

059648627

ABSTRACT:
A CPU (central processing unit) of a computer. The CPU comprises a dispatch controller, a pipeline, a working register file, and an architectural register file. The dispatch controller dispatches instructions for execution and determines whether the dispatched instructions are valid or invalid. The pipeline executes the dispatched instructions using selected operands in the pipeline and generates operands in response. The working register file stores the generated operands before the executed instructions are determined to be valid or invalid by the dispatch controller such that the stored operands may be subsequently selected for use in executing an instruction in the pipeline. The architectural register file stores the generated operands for those of the executed instructions that are determined to be valid by the dispatch controller and transfer operands currently stored therein when one of the executed instructions is determined to be invalid by the dispatch logic. The working register file then stores the transferred operands such that the transferred operands may be subsequently selected for use in executing an instruction in the pipeline.

REFERENCES:
patent: 5226142 (1993-07-01), Vegesna et al.
patent: 5535346 (1996-07-01), Thomas, Jr.
patent: 5630157 (1997-05-01), Dwyer, III
patent: 5764942 (1998-06-01), Kahle et al.
patent: 5790827 (1998-08-01), Leung

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