Electrical computers and digital processing systems: processing – Processing architecture – Data driven or demand driven processor
Reexamination Certificate
2006-10-17
2006-10-17
Pan, Daniel H. (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Data driven or demand driven processor
C712S248000
Reexamination Certificate
active
07124280
ABSTRACT:
An execution control apparatus of a data driven information processor includes: an instruction decoder that outputs the a number of inputs of an instruction; a waiting data storage region that stores N (N≧2) waiting data and respective data valid flags in one address; a constant storage that stores constants and a constant valid flag; a constant readout unit that reads out a constant and a constant valid flag from the constant storage with the node number of an input packet as the address; a unit that calculates a hash address and selects a process for data waiting depending upon a combination of a data valid flag, a constant valid flag, and the number of instuction inputs; and a unit that performs a waiting process in response to a select signal.
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Hatakeyama Kouichi
Kamitani Shingo
Birch, Stewart, Kolasch and Birch, LLP.
Pan Daniel H.
Sharp Kabushiki Kaisha
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