Executing speculative parallel instructions threads with forking

Details Executing speculative parallel instructions threads with forking Executing speculative parallel instructions threads with forking

1995-02-03

1998-09-22

Lall, Parshotam S.

395376, 395391, 395562, 395676, 39580023, G06F 930, G06F 938

Patent

active

058128115

ABSTRACT:
A central processing unit (CPU) in a computer that permits speculative parallel execution of more than one instruction thread. The CPU uses Fork-Suspend instructions that are added to the instruction set of the CPU, and are inserted in a program prior to run-time to delineate potential future threads for parallel execution. The CPU has an instruction cache with one or more instruction cache ports, a bank of one or more program counters, a bank of one or more dispatchers, a thread management unit that handles inter-thread communications and discards future threads that violate dependencies, a set of architectural registers common to all threads, and a scheduler that schedules parallel execution of the instructions on one or more functional units in the CPU.

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