Executing partial-width packed data instructions

Details Executing partial-width packed data instructions Executing partial-width packed data instructions

2005-05-09

2008-12-16

Tsai, Henry W. H. (Department: 2184)

Electrical computers and digital processing systems: processing

Processing architecture

Vector processor

C712S005000, C712S020000, C712S022000, C712S023000, C712S027000

Reexamination Certificate

active

07467286

ABSTRACT:
A method and apparatus are provided for executing packed data instructions. According to one aspect of the invention, a processor includes registers, a register renaming unit coupled to the registers, a decoder coupled to the register renaming unit, and a partial-width execution unit coupled to the decoder. The register renaming unit provides an architectural register file to store packed data operands that include data elements. The decoder is to decode a first and second set of instructions that each specify one or more registers in the architectural register file. Each of the instructions in the first set specify operations to be performed on all of the data elements. In contrast, each of the instructions in the second set specify operations to be performed on only a subset of the data elements. The partial-width execution unit is to execute operations specified by either the first or second set of instructions.

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