Executing partial-width packed data instructions

Details Executing partial-width packed data instructions Executing partial-width packed data instructions

1998-03-31

2000-09-19

Coleman, Eric

Electrical computers and digital processing systems: processing

Architecture based instruction processing

712 22, 712 23, G06F 930

Patent

active

061227250

ABSTRACT:
A method and apparatus are provided for executing scalar packed data instructions. According to one aspect of the invention, a processor includes a plurality of registers, a register renaming unit coupled to the plurality of registers, and a decoder coupled to the register renaming unit. The register renaming unit provides an architectural register file to store packed data operands each of which include a plurality of data elements. The decoder is configured to decode a first and second set of instructions (e.g., a set of full-width packed data instructions and a set of partial-width packed data instructions) that each specify one or more registers in the architectural register file. Each of the instructions in the first set of instructions specify operations to be performed on all of the data elements stored in the one or more specified registers. In contrast, each of the instructions in the second set of instructions specify operations to be performed on only a subset of the data element stored in the one or more specified registers.

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