Executing computer instrucrions by circuits having different lat

Boots – shoes – and leggings

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G06F 738

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058448306

ABSTRACT:
A computer instruction execution unit includes different execution paths for different categories of instructions. Different execution paths share circuitry. The slower execution paths are pipelined. In some embodiments, all execution paths are pipelined. Fast instructions are executed by a fast execution path. Slower instructions are executed by a slower execution path. Faster instructions immediately following the slower instruction are also executed by the slower execution path not to block the shared circuitry. Consequently, the throughput is increased and the average instruction execution latency is reduced. When a sufficient number of clock cycles occur with no instructions started, subsequent fast instructions are executed by the fast execution path.

REFERENCES:
patent: H1222 (1993-08-01), Brown et al.
patent: 4217657 (1980-08-01), Handly et al.
patent: 4488252 (1984-12-01), Vassar
patent: 4589067 (1986-05-01), Porter et al.
patent: 4683547 (1987-07-01), DeGroot
patent: 4777613 (1988-10-01), Shahan et al.
patent: 4839846 (1989-06-01), Hirose et al.
patent: 4926369 (1990-05-01), Hokenek et al.
patent: 4941120 (1990-07-01), Brown et al.
patent: 4999802 (1991-03-01), Cocanougher et al.
patent: 5117384 (1992-05-01), Drehmel et al.
patent: 5136536 (1992-08-01), Ng
patent: 5204825 (1993-04-01), Ng
patent: 5241490 (1993-08-01), Poon
patent: 5247471 (1993-09-01), Hilker et al.
patent: 5257215 (1993-10-01), Poon
patent: 5260889 (1993-11-01), Palaniswami
patent: 5267186 (1993-11-01), Gupta et al.
patent: 5272660 (1993-12-01), Rossbach
patent: 5282156 (1994-01-01), Miyoshi et al.
patent: 5301139 (1994-04-01), Zinger
patent: 5310134 (1994-05-01), Hsu et al.
patent: 5317527 (1994-05-01), Britton et al.
patent: 5337265 (1994-08-01), Desrosiers et al.
patent: 5343413 (1994-08-01), Inoue
patent: 5357455 (1994-10-01), Sharangpani et al.
patent: 5390134 (1995-02-01), Heikes et al.
patent: 5463574 (1995-10-01), Desrosiers et al.
patent: 5481686 (1996-01-01), Dockser
patent: 5493520 (1996-02-01), Schmookler et al.
patent: 5504912 (1996-04-01), Morinaga et al.
patent: 5511016 (1996-04-01), Bechade
patent: 5528525 (1996-06-01), Suzuki
Benschneider, et al., "A Pipelined 50-MHz CMOS 64-bit Floating-Point Arithmetic Processor", IEEE Journal of Solid-State Circuits, vol. 24, No. 5, Oct. 1989, pp. 1317-1323.
Quach, et al., "An Improved Algorithm for High-Speed Floating-Point Addition", Stanford University Technical Report No. CSL-TR-90-442, Aug. 1990, pp. 1-17.
Hokenek, et al., "Second-Generation RISC Floating Point with Multiply-Add Fused", IEEE Journal of Solid-State Circuits, vol. 25, No. 5, Oct. 1990, pp. 1207-1213.
Ide, et al., "A 320-MFLOPS CMOS Floating-Point Processing Unit for Superscalar Processors", IEEE Journal of Solid-State Circuits, vol. 28, No. 3, Mar. 1993, pp. 352-361.
Encyclopedia of Computer Science & Engineering, Second Edition, Van Nostrand Reinhold Co., New York, NY, 1983, pp. 98-102, 1322-1324.
Gwennap, et al., "UltraSparc Unleashes SPARC Performance, Next-Generation Design Could Put Sun Back in Race" Microprocessor Report, vol. 8, No. 13, Oct. 3, 1994, pp. 1-10.
Hokenek et al., "Leading-Zero Anticipator (LZA) in the IBM RISC System/6000 Floating-Point Execution Unit," IBM J. Res. Develop., vol. 34, No. 1, Jan., 1990, pp. 71-77.
Montoye, et al., "Design of the IBM RISC System/6000 Floating-Point Execution Unit," IBM J. Res. Develop., vol. 34, No. 1, Jan. 1990, pp. 59-70.
LSI Logic Databook and Design Manual, 5th Ed., HCMOS Macrocells, Macrofunctions, Oct. 1986, pp. 12-1 to 12-28.
Quach et al., "Leading One Prediction--Implementation, Generalization, and Application, Technical Report: CSL-TR-91-463," Computer System Laboratory, Stanford University, Mar. 1991, pp. 1-12.
"IEEE Standard for Binary Floating-Point Arithmetic," Institute of Electrical and Electronics Engineers, Inc., New York, NY, ANSI/IEEE Std. 754, Nov. 1994, pp. 1-18.
"IC Master 3. Advertisers Technical Data; LSI Logic Products and Services," Hearst Business Communications, Inc., IC Master, 1991, pp. 3529-3532.
The SPARC Architecture Manual, Version 8, (SPARC International, Inc., Prentice-Hall, Inc., New Jersey, 1992), pp. 1-316.
Kahan, W., et al., "A Proposed IEEE-CS Standard for Binary Floating Point Arithmetic", Proceedings of the computer Science and Statistics: 12th Annual Symposium on the Interface, May 10-11, 1979, University of Waterloo, Waterloo, Ontario, Canada, pp. 32-36.
Yu, R.K., et al., "167 Mhz Radix-4 Floating Point Multiplier", Proceedings of the Twelfth Symposium on Computer Arithmetic (IEEE 1995), pp. 149-154.
Weste, Neil H.E., et al., "Principles of CMOS VLSI Design--A Systems Perspective" (Addison-Wesley Publishing Co., 2nd Ed., 1993), p. 532.
Hicks, T.N., et al., "POWER2 Floating-Point Unit: Architecture and Implementation", IBM J. Res. Develop., vol. 38, No. 5, Sep. 1994, pp. 525-536.
Omondi, A.R., "Computer Arithmetic Systems: Algorithms, Architecture and Implementation", 1994, pp. 76-86.

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