Electrical computers and digital processing systems: processing – Processing architecture – Microprocessor or multichip or multimodule processor having...
Reexamination Certificate
1998-09-28
2001-05-22
Pan, Daniel H. (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Microprocessor or multichip or multimodule processor having...
C712S210000, C712S248000, C711S102000, C711S103000
Reexamination Certificate
active
06237080
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to executable programs and in particular to a method and apparatus for storing and using executable programs.
BACKGROUND OF THE INVENTION
At the heart of most modern electronic devices is a microprocessor or central processing unit which operates in accordance with a set of software operating instructions which together form an executable program. The instructions are stored in a digital memory which may be internal to the microprocessor or, as is more usually the case, externally connected to the microprocessor. The set of operating instructions generally define the basic input/output system (BIOS) of the microprocessor together with device drivers, libraries, and user applications.
Software instructions defining the basic operation of a microprocessor are usually stored in non-volatile read only memory (ROM). Until recently, the preferred choice for storing operating instructions was UV light erasable programmable read only memory. More recently however, the preferred choice for storing operating instructions, especially in embedded devices (e.g. mobile phones, personal digital assistants, etc) has become flash ROM. Flash ROM is both non-volatile and electrically erasable and is used, to a large extent, because it can be programmed following assembly of the PCB containing the flash ROM oar of the completed device. A further advantage is that it is possible to upgrade operating instruction stored in the flash ROM at some future date.
Compared to conventional ROM, flash ROM remains expensive. There therefore exists a desire to reduce the amount of flash ROM used in individual products. Furthermore, accessing flash ROM is relatively slow, significantly reducing the performance of electronic devices. Conventional computer architectures rely upon a complex instruction set computer (CISC) architecture. This utilises a large number (e.g. 1000) of instructions which define very specific tasks. The instructions are of variable length and are decoded by the computer's CPU before execution. There is described in Japanese non-examined patent publication no. 55-131848 a data processing unit which comprises a central processing unit, a main memory unit, and an external memory unit. A compressed program is stored in the external memory unit and, before commencing processing operations, the compressed program is read from the external memory unit in blocks and decompressed. The decompressed program is then written to the main memory unit. However, the compression ratio which can be achieved with CISC code is relatively low and it is not believed that the disclosure of JP-131848 has been widely used.
SUMMARY OF THE INVENTION
The present invention flows from the recognition that the new generation of reduced instruction set computers (RISC) make use of a much reduced set of instructions. In addition, RISC architectures have a generally fixed length instruction size, allowing the use of hard-wired decoding logic.
According to a first aspect of the present invention there is provided a method of operating apparatus having a central processing unit (CPU) with a reduced instruction set computer (RISC) architecture, and a read only memory (ROM), the method comprising reading a set of compressed RISC operating instructions from the ROM into the CPU, decompressing the compressed instructions in the CPU, and thereafter operating the apparatus in accordance with the decompressed instructions.
The present invention makes it possible to make a considerable saving in the amount of ROM memory required for storing RISC operating instructions for a central processing unit. As the set of different possible RISC instructions is relatively small (e.g. around 250) compared to the total number of instructions (e.g. around 1000,000), instructions tend to be repeated many times and therefore the degree of compression which can be achieved is high. Although extra RAM may be required, a considerable cost saving may be achieved where expensive ROM is replaced by cheap RAM. Furthermore, manufacturing times may be reduced as it only becomes necessary to write a relatively short program to the ROM memory, rather than a long uncompressed program.
According to a second aspect of the present invention there is provided a method of operating apparatus having a central processing unit (CPU) and a read only memory (ROM), the method comprising reading a set of compressed operating instructions from the ROM into the CPU, decompressing the compressed instructions in the CPU, and thereafter operating the apparatus in accordance with the decompressed instructions, the method further comprising generating one or more replacement or additional compressed instructions in the CPU and writing the compressed instruction(s) to the ROM.
The above second aspect of the present invention makes it possible to amend the stored compressed instructions in a dynamic manner. This may, for example, allow a user to configure the computer according to his specific needs.
Preferably, the method comprises the step of reading a set of operating instructions from the ROM into the CPU, which instructions define a program for compressing said replacement or additional instruction(s). More preferably, the instructions defining the compression program form part of said set of compressed operating instructions.
Preferably, the method of the above first or second aspect of the invention comprises writing the decompressed instruction set to a random access memory (RAM). Thereafter, the decompressed instructions are read from the RAM by the CPU. It is noted that RAM typically offers high access speeds compared to slow (e.g. flash) ROM memory, giving a significant increase in system performance. In this case, increased speed also offers reduced power consumption compared to systems which use slow ROM memory and in which power is consumed even when the system is waiting to access the ROM.
According to a third aspect of the present invention there is provided apparatus having a central processing unit (CPU) a reduced instruction set computer (RISC) architecture, and a read only memory (ROM), there being stored in the ROM a set of compressed RISC operating instructions, the CPU being arranged in use to read the compressed instructions from the ROM, to decompress these instructions, and subsequently to operate the apparatus in accordance with the decompressed instructions.
According to a fourth aspect of the present invention there is provided apparatus comprising a central processing unit (CPU), a read only memory (ROM), and a set of compressed operating instructions stored in the ROM, the CPU being arranged in use to read the compressed instructions from the ROM, decompress the compressed instructions, and thereafter operate the apparatus in accordance with the decompressed instructions, the apparatus being further arranged in use to compress replacement or additional operating instructions and to write these compressed instructions to the ROM.
Preferably, said ROM memory is flash ROM memory.
Preferably, the apparatus comprises a random access memory which, in use, is arranged to store the operating instructions following decompression by the CPU.
Apparatus according to the above third and fourth aspects of the invention may advantageously be incorporated into mobile communication devices such as mobile telephones and combined mobile telephone/personal digital assistants.
REFERENCES:
patent: 5315638 (1994-05-01), Mukari
patent: 5619698 (1997-04-01), Lillich et al.
patent: 5671413 (1997-09-01), Shipman et al.
patent: 5799165 (1998-08-01), Favor et al.
patent: 5953502 (1999-09-01), Helbig, Sr.
patent: 6044450 (2000-03-01), Tsuhima et al.
patent: 55-131848 (1980-10-01), None
patent: WO 94/19768 (1994-01-01), None
patent: WO 95/27244 (1995-10-01), None
Patent Abstracts Of Japan—Publication No. 07248921, vol. 96, No. 1, 1996.
“Algorithm To Allow A Computer System's BootROM In Compressed Form”, IBM Technical Disclosure Bulletin, vol. 37, No. 4B, pp 571-572, 1994.
“Blockweise Loeschbar”, Elektronik, vol. 40
Nokia Mobile Phones Ltd.
Pan Daniel H.
Perman & Green LLP
LandOfFree
Executable programs does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Executable programs, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Executable programs will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2490909