Patent
1992-05-18
1994-12-27
Richardson, Robert L.
395425, G11B 1300
Patent
active
053773241
DESCRIPTION:
BRIEF SUMMARY
FIELD OF THE INVENTION
The present invention relates to an exclusive control system on the side of a shared storage of a multiprocessor system in which a plurality of processor modules and a plurality of shared storage modules are connected together by a system bus.
BACKGROUND OF THE INVENTION
Normally, necessary instructions and data to be used by a processor are stored in a shared storage of a multiprocessor system, Each of the processor modules frequently accesses the shared storage. In this connection, exclusive instructions are indispensable for accesses to a shared storage, and among them is a CSI (compare and store interlocked) instruction for substituting or rewriting data when it is determined that data read from a shared storage coincides with the data expected by software. However, when a CSI instruction is executed, an exclusive control is performed such that a system bus between a processor module and a shared storage module is exclusively occupied until the end of the instruction. During the execution of the CSI instruction, no other processor modules are permitted to access the system bus, thereby greatly reducing the system performance. Therefore, it is requested that the range of the exclusive control and the time taken for it to execute a CSI instruction are limited to the least possible extent.
As shown in FIG. 20, a conventional multiprocessor system forms a computer system referred to as a multiprocessor system in which a plurality of processor modules 10 and a plurality of shared storage modules 12 are connected through a system bus 16 for transmitting data.
Thus, exclusive instructions are required to access a shared storage in a multiprocessor system, and a CSI instruction is one of them.
As shown in FIG. 21, the operation sequence of a CSI instruction is fixed such that, when the data of a certain address at which the shared storage comprising a plurality of shared storage modules (SSM) 12 is located are to be rewritten, access address data can be read and actually rewritten if the read data coincides with the data anticipated by a central processing unit (.mu.P) 18 of the processor module 10 to be stored at the access address.
After the access address data are read, the CSI instruction performs exclusive control so that another central processing unit 18 in other processor modules 10 cannot access and update the access address while the comparison results in coincidence and the address data are rewritten.
DISCLOSURE OF THE INVENTION
The conventional exclusive control of a shared storage during the execution of a CSI instruction covers all the path from a central processing unit 18 in an accessing processor module 10 to a shared storage module 12 to be accessed through the system bus 16 in a shared storage space as shown by the bold line in FIG. 20. Additionally, the exclusive control spans a long time in reading, comparing, and writing data.
During the exclusive control, other central processing unit 10 in other processor modules 10 cannot access the shared storage module 12. Therefore, the CSI instruction has been a cause of great deterioration in system performance.
The present invention has been developed to solve this problem and aims at providing a shared storage exclusive control method for improving the system performance by limiting the range and shortening the time of the exclusive control of a shared storage by a CSI instruction.
FIG. 1 is a block diagram for explaining the principle of the present invention.
As shown in FIG. 1, the present invention relates to a computer system comprising one or more processing modules (processor modules) 10 each having at least a local storage 20, a central processing unit 18, and a connection unit 22 for connection to a system bus 16, and one or more shared storage modules 12 each having at least a shared storage unit 26 and a connection unit 28 for connection to the system bus 16.
In this computer system, the present invention has the connection unit 28 in the shared storage module 12 for recognizing a CSI instruction to read
REFERENCES:
patent: 5201039 (1993-04-01), Sakamura
Kabemoto Akira
Ogawa Toshio
Shirotani Masashi
Fujitsu Limited
Richardson Robert L.
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