Exclusive or circuit and parity checking circuit incorporating t

Excavating

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

307471, G06F 1110, H03K 1921

Patent

active

044307373

ABSTRACT:
An Exclusive OR circuit with at least two inputs (1 and 2) which exhibits a good immunity to noise. The circuit comprises diodes (D1 and D2) and two transistors (T1 and T2) which have their emitters connected to a reference voltage VR and produce AB at C1. Transistors (T 14 and T5) produce AB at C2, and output transistors (T13 and T6) produce ##STR1## at 3. This circuit can advantageously be used to realize a parity checking circuit.

REFERENCES:
patent: 3129406 (1964-04-01), Perley
patent: 3309666 (1967-03-01), Frohman
patent: 3649844 (1972-03-01), Kroos
patent: 4328435 (1982-05-01), Case
IBM Technical Disclosure Bulletin, "MTL Exclusive OR Circuit", G. J. Robbins, vol. 19, No. 6, Nov. 1976, p. 2077.
G. E. Hack, Even-Odd Circuit, IBM Technical Disclosure Bulletin, vol. 7., No. 6, Nov. 1964, pp. 425-426.
IBM Technical Disclosure Bulletin, "Gated Two-Way Exclusive `OR` Trigger" by O. J. Bedrij, vol. 2, No. 6, Apr. 1970, p. 51.
IBM Technical Disclosure Bulletin, "Gated Exclusive OR Circuit", F. H. Lohrey et al., vol. 19, No. 6, Nov. 1976, p. 2080.
IBM Technical Disclosure Bulletin, "Exclusive `OR` Circuit" by R. C. Greenhalgh, vol. 2, No. 6, Apr. 1960, pp. 98-99.
IBM Technical Disclosure Bulletin, "Cascode Exclusive OR", J. E. Gersbach, vol. 19, No. 6, Nov. 1976, pp. 2010-2011.
IBM Technical Disclosure Bulletin, "Three-Level Exclusive OR" by W. H. McAnney, vol. 4, No. 7, Dec. 1961, pp. 58-59.
IBM Technical Disclosure Bulletin, "Exclusive OR Shift Circuit" by J. W. Delmege, Jr., vol. 5, No. 1, Jun. 1962, p. 63.
IBM Technical Disclosure Bulletin, "Exclusive OR Input Decoders for PLA", P. S. Balasubramanian et al., vol. 20, No. 6, Nov. 1977, pp. 2308-2309.
IBM Technical Disclosure Bulletin, "Three Transistor Exclusive OR Circuit", L. J. Patterson, vol. 5, No. 8, Jan. 1963, pp. 38-39.
IBM Technical Disclosure Bulletin, ""4-Way Exclusive OR", A. Weinberger, vol. 20, No. 8, Jan. 1978, pp. 3220-3222.
IBM Technical Disclosure Bulletin, "One Transistor, Exclusive OR Circuit" by I. G. Akmenkalns, vol. 5, No. 12, May 1963, pp. 65-66.
IBM Technical Disclosure Bulletin, "Two-Level Not Exclusive OR", L. J. Boland, vol. 7, No. 9, Feb. 1965, pp. 743-744. _
IBM Technical Disclosure Bulletin, "Error Detecting Circuit For Open Input Terminals", G. A. Maley et al., vol. 21, No. 7, Dec. 1978, pp. 2806-2808.
IBM Technical Disclosure Bulletin, "Logic Level Equal-Compare Circuit", L. J. Wallace, vol. 8, No. 2, Jul. 1965, p. 330.
IBM Technical Disclosure Bulletin, "Summing of Exclusive-OR Terms Having a Common Factor by Converting to a Single XOR", A. Weinberger, vol. 22, No. 1, Jun. 1979, pp. 234-236.
IBM Technical Disclosure Bulletin, "Exclusive-OR Circuit", A. Kuck et al., vol. 8, No. 4, Sept. 1965, p. 672.
IBM Technical Disclosure Bulletin, "Inverse Exclusive-OR Circuit", T. S. Jen, vol. 8, No. 8, Jan. 1966, pp. 1156-1157.
IBM Technical Disclosure Bulletin, "High Speed Exclusive-OR Circuit", R. L. Ehrlickman, vol. 22, No. 6, Nov. 1979, p. 2291.
IBM Technical Disclosure Bulletin, "Exclusive-OR Circuit", D. W. Murphy, vol. 8, No. 11, Apr. 1966, p. 1660.
IBM Technical Disclosure Bulletin, "Exclusive OR Circuit", Z. T. Dearden et al., vol. 23, No. 2, Jul. 1980, pp. 684-685.
IBM Technical Disclosure Bulletin, "Exclusive-OR Complement Circuit", P. J. Evans, vol. 9, No. 9, Feb. 1967, pp. 1210-1211.
IBM Technical Disclosure Bulletin, "Parallel-Reset Shift Register With Exclusive-OR Latches", J. J. Kennedy, et al., vol. 1, No. 9, Feb. 1969, p. 1133-1134.
IBM Technical Disclosure Bulletin, "Exclusive OR Output Latch for PLA", P. S. Balasubramanian et al., vol. 20, No. 6, Nov. 1977, pp. 2310-2311.
IBM Technical Disclosure Bulletin, "Four-Way Exclusive-OR", J. E. Gersbach, vol. 11, No. 9, Feb. 1969, pp. 1162-1163.
IBM Technical Disclosure Bulletin, "T.sup.2 L Exclusive OR", F. Montegari, vol. 19, No. 9, Feb. 1977, p. 3430.
IBM Technical Disclosure Bulletin, "Exclusive-OR Logic", R. T. sha, vol. 12, No. 8, Jan. 1970, pp. 1287-1288.
IBM Technical Disclosure Bulletin, "Exclusive-OR Circuit", J. Villejoubert, vol. 12, No. 9, Feb. 1970, p. 1469.
IBM Technical Disclosure Bulletin, "Exclusive OR Circuit Conditioned by a Plurality of Gates", J. Brandon, vol. 19, No. 10, Mar. 1977, pp. 3761-3762.
IBM Technical Disclosure Bulletin, "Integrated Circuit Exclusive-OR Circuit", W. Rosenbluth, vol. 12, No. 11, Apr. 1970, p. 1766.
IBM Technical Disclosure Bulletin, "Three-Device Exclusive OR Circuit", P. S. Balasubramanian et al., vol. 20, No. 10, Mar. 1978, pp. 4014-4015.
IBM Technical Disclosure Bulletin, "Exclusive-OR Circuit", J. A. Palmieri et al., vol. 13, No. 5, Oct. 1970, p. 1074.
IBM Technical Disclosure Bulletin, "Bootstrap FET `OR` Circuit", W. M. Smith, Jr., vol. 13, No. 7, Dec. 1970, p. 1815.
IBM Technical Disclosure Bulletin, "Unverted XOR Circuit", A. Brunin, vol. 21, No. 5, Oct. 1978, p. 1913.
IBM Technical Disclosure Bulletin, "Exclusive OR Data Manipulation For Cyclic Code Generation", J. D. Dixon, vol. 14, No. 3, Aug. 1971, p. 857.
IBM Technical Disclosure Bulletin, "Exclusive OR Circuit", A. Y. Chang et al., vol. 22, No. 2, Jul. 1979, pp. 593-594.
IBM Technical Disclosure Bulletin, "Exclusive OR Set Latch", C. W. Hannaford, vol. 14, No. 9, Feb. 1972, pp. 2827-2828.
IBM Technical Disclosure Bulletin, "Dynamic FET Half-Cycle Delay Exclusive OR Circuit", S. C. Pi, vol. 14, No. 12, May 1972, p. 3648.
IBM Technical Disclosure Bulletin, "Bipolar Selector Functions", R. T. Dennison et al., vol. 23, No. 5, Oct. 1980, pp. 1913-1914.
IBM Technical Disclosure Bulletin, "Two-Way Exclusive `OR` Using Complementary FETs", S. P. Bennett, vol. 16, No. 3, Aug. 1973, p. 1007.
IBM Technical Disclosure Bulletin, "Exclusive OR Circuit(XOR)", G. J. Gaudenzi, vol. 16, No. 10, Mar. 1974, p. 3249.
IBM Technical Disclosure Bulletin, "NPN-PNP Exclusive OR", F. A. Montegari, vol. 23, No. 10, Mar. 1981, p. 4502.
IBM Technical Disclosure Bulletin, "Inverse Exclusive OR Circuit For Dynamic Logic", L. R. Lau et al., vol. 17, No. 6, Nov. 1974, pp. 1666-1667.
IBM Technical Disclosure Bulletin, "Odd/Even Shunt Circuits", M. P. Marcus, vol. 17, No. 8, Jan. 1975, pp. 2234-2236.
IBM Technical Disclosure Bulletin, "Exclusive OR Invert Circuit", P. Debord et al., vol. 18, No. 1, Jun. 1975, p. 137.
IBM Technical Disclosure Bulletin, "Parity Check Circuit Arrangement For Random-Access Memory Array", C. Marzin et al., vol. 18, No. 5, Oct. 1975, pp. 1411-1412.
IBM Technical Disclosure Bulletin, "Four-Bit Exclusive OR Circuit", J. C. Leininger, vol. 18, No. 6, Nov. 1975, pp. 1681-1682.
IBM Technical Disclosure Bulletin, "Antisaturation Clamp For XOR Circuit", D. Swietek, vol. 18, No. 8, Jan. 1976, p. 2508.
IBM Technical Disclosure Bulletin, "Logical Circuit", Y. M. Ting, vol. 18, No. 9, Feb. 1976, p. 2882.
IBM Technical Disclosure Bulletin, "Single-Cell Exclusive OR Circuit", E. B. Eichelberger et al., vol. 18, No. 9, Feb. 1976, pp. 2892-2893.
IBM Technical Disclosure Bulletin, "Exclusive OR Circuit", A. A. Hansen, vol. 19, No. 4, Sept. 1976, pp. 1235-1236.
IBM Technical Disclosure Bulletin, "Bubble Domain Exclusive OR Gate", H. J. Yu, vol. 19, No. 5, Oct. 1976, pp. 1932-1933.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Exclusive or circuit and parity checking circuit incorporating t does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Exclusive or circuit and parity checking circuit incorporating t, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Exclusive or circuit and parity checking circuit incorporating t will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2165010

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.