Excessive error correction control

Details Excessive error correction control Excessive error correction control

1991-04-17

1993-12-28

Atkinson, Charles E.

Excavating

371 13, 371 216, G06F 1110

Patent

active

052746461

ABSTRACT:
A method of automatically invoking a recoverable and fault tolerant implementation of the complemented/recomplemented (C/R) error correction method without the assistance of a service processor when an excessive error is detected in main storage (MS) by ECC logic circuits. An excessive error is not correctable by the ECC. These novel changes to the C/R method increase its effectiveness and protect the C/R hardware against random failure. Further, if an excessive error is corrected in a page in MS, an excessive error reporting process is provided for controlling the reporting using a storage map to determine if a previous correction in that page has been reported. If it has been reported, then no further reporting of soft excessive errors is made for that page. A service processor is signaled in parallel to update its persistent copy of the storage map so that on a next initializations of MS the memory map can be restored in the memory. The memory map is used to assist the repair of failing parts of MS, and is reset after MS is repaired.

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patent: 4964129 (1990-10-01), Bowden, III et al.
patent: 5058115 (1991-10-01), Blake et al.

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