Coded data generation or conversion – Analog to or from digital conversion – Differential encoder and/or decoder
Reexamination Certificate
2000-03-22
2002-07-02
JeanPierre, Peguy (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Differential encoder and/or decoder
C341S144000
Reexamination Certificate
active
06414615
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
This invention relates to analog-to-digital converters. Specifically, the present invention relates to high-performance delta sigma analog-to-digital converters.
2. Description of the Related Art
Analog-to-digital converters (ADC's) are employed in a variety of demanding applications including computer modems, wireless telephones, and satellite receiver systems. Such applications demand cost-effective ADC's that can efficiently convert an analog input signal to digital output signal over a wide range of frequencies and signal magnitudes with minimal noise and distortion.
An ADC typically converts an analog signal to a digital signal by sampling the analog signal at predetermined sampling intervals and generating a sequence of binary numbers via a quantizer in response thereto. The sequence of binary numbers is a digital signal representation of the sampled analog signal.
The length of a binary number assigned to a given sampled value of the analog signal corresponds to the number of quantizer bits and is limited. Consequently, a digital sample will not always precisely represent the corresponding analog sample. The difference between a digital sample and the corresponding analog sample represents quantization error.
The sampling frequency of the ADC is the inverse of the sampling interval. The resolution of the ADC is directly related to the number of binary bits assigned to each sampled value and inversely related to quantization error. The minimum difference between successive values that may be represented by the quantizer is the quantization step size. Quantization error results in quantization noise in the output digital signal, which is also called granular noise.
When an analog sample is too large to be accurately digitally represented by to the quantizer (given the fixed number of quantizer bits), clipping occurs, resulting in distortion called overload noise. To reduce overload noise, the dynamic range of an ADC is often increased. The dynamic range of an ADC is the range of values of an analog input signal over which the ADC can accurately represent the analog signal. For a conventional Nyquist ADC, the dynamic range is difference between maximum and minimum values represented by the quantizer. High-quality ADC's often have high signal-to-noise ratios (SNR's) and high dynamic ranges.
The sampling frequency of an ADC is usually chosen to be greater than twice the maximum frequency of the analog input signal, which is known as the Nyquist rate. In a typical Nyquist ADC, the input analog signal is sampled at approximately the Nyquist rate. To achieve effective SNR'S, the resolution of the ADC is increased.
Unfortunately, adding additional resolution required to obtain sufficient SNR's is often costly.
Alternatively, oversampling ADC's are employed. An oversampling ADC samples an analog signal at sufficiently high rates to reduce quantizer resolution requirements. By oversampling, differences between signal values of successive samples are reduced, which reduces resolution requirements. Unfortunately, typical oversampling ADC's are still particularly susceptible to overload distortion and granular noise.
A delta sigma (&Dgr;&Sgr;) modulator ADC (&Dgr;&Sgr; ADC) sufficiently oversamples a given analog input signal so that only one quantizer bit is required. Some &Dgr;&Sgr; ADC's however, employ multi-bit quantizers to fuirther reduce quantization noise. A continuous time &Dgr;&Sgr; ADC (also known as a sigma-delta modulator ADC) typically includes a continuous time loop filter having integrators and transconductance amplifiers, which implements a bandpass loop filter and/or resonator, to reduce granular noise and overload distortion. The &Dgr;&Sgr; ADC includes one or more feedback loops, which include multi-bit feedback DAC's, to avoid the accumulation of quantization errors and to stabilize the &Dgr;&Sgr; ADC.
Unfortunately, conventional &Dgr;&Sgr; ADC's are often difficult to implement and are susceptible to noise resulting from delays in the quantizer feedback path. The delays include signal dependent jitter delay, latch delay, and DAC cell switching delays. To compensate for the excess latch delay, a plurality of additional multi-bit return-to-zero (RZ) digital-to-analog converters (DAC's) are selectively placed in the quantizer feedback path. (The RZ DAC's are DAC's whose outputs periodically reset to zero.) However, the additional RZ DAC's are often expensive and difficult to implement accurately. At the high sampling rates required for &Dgr;&Sgr; ADC's, the RZ DAC's in the quantizer feedback path may have insufficient time to settle to zero, resulting in poor ADC performance. For performance reasons, more cost-effective non-return-to-zero (NRZ) DAC's are typically not substituted in place of the RZ DAC's in conventional &Dgr;&Sgr; ADC designs.
In an alternative approach, some feedback delays are compensated via a combination of non-delayed and half-delayed appropriately tuned feedback DAC's. However, this approach still fails to effectively compensate for signal dependent jitter and other delays.
Finite DAC cell switching delays in the multi-bit feedback DAC's are also problematic. As is known in the art, multi-bit DAC's have hardware limitations that result in glitches in signal output by circuits employing these devices. Glitches result when less than all of the bits in a DAC change simultaneously. Hence, the output waveform exhibits temporary false values as the bits change to their appropriate values. The glitches cause spurious frequency tones, i.e., glitch noise, to appear at the DAC output very close to the desired output frequency. The spurious tones can degrade the performance of the accompanying &Dgr;&Sgr; ADC. Unmatched DAC cell switching delays reduce the dynamic range of the accompanying &Dgr;&Sgr; ADC and adversely affect circuit stability, especially in fourth order or higher order &Dgr;&Sgr; ADC's. The order of a given &Dgr;&Sgr; ADC is related to the number of resonating frequencies in the loop filter of the &Dgr;&Sgr; ADC.
The output of a feedback DAC also includes quantization noise that is directly related to the DAC's amplitude resolution. The number of bits used in the DAC computations determines amplitude resolution. DAC's with excellent amplitude resolution and frequency response tend to consume excess power and are expensive. In addition, spurious tones become more problematic as the frequency of the periodic signal increases. This further limits the range of allowable output frequencies.
Some conventional &Dgr;&Sgr; ADC's employ a high-speed flash quantizer, which includes multiple comparators for comparing sampled signal values to particular reference thresholds corresponding to quantization levels. A given sampled signal value is closer to the thresholds of some comparators than others. Consequently, the quantizer comparators switch and regenerate at different times, which results in undesirable signal dependent jitter delay.
Conventional &Dgr;&Sgr; ADC's employing RZ DAC's often fail to address signal dependent jitter. Signal dependent jitter is an additional source of loop delay in the quantizer feedback path. The additional loop delay reduces the dynamic performance of the ADC and may reduce feedback loop stability. An ADC with good dynamic performance accurately represents a given analog signal over a wide range of values and frequencies.
Hence, a need exists in the art for a cost-effective high-performance &Dgr;&Sgr; ADC that effectively compensates for quantizer feedback loop delays, including signal dependent jitter, latch delay, and finite DAC cell switching delay.
SUMMARY OF THE INVENTION
The need in the art is addressed by the high-performance analog-to-digital converter of the present invention. In the illustrative embodiment, the inventive analog-to-digital converter is a delta sigma modulator analog-to-digital converter and includes a f
Alkov Leonard A.
Jean-Pierre Peguy
Lauture Joseph
Raytheon Company
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