Exception handling processor for handling first and second level

Details Exception handling processor for handling first and second level Exception handling processor for handling first and second level

1990-03-21

1993-08-17

Lee, Thomas C.

Boots, shoes, and leggings

3642295, 3642412, 36424345, 3642421, 3642415, 3642416, 3642425, 3642462, 3642597, 3642595, 3642598, 3642596, 3642613, 3642614, 3642615, 364DIG1, G06F 930, G06F 942, G06F 946, G06F 1318

Patent

active

052377008

ABSTRACT:
A processor having improved exception handling capability handles second level exceptions with reduced exception latency. The processor processes instructions in order through a plurality of serial stages. A first set of registers continuously tracks each instruction as it advances from stage to stage. An exception handles processes first level exception conditions and precludes updating of the first set of registers when it processes first level exception conditions to permit the processor to restart at the point of a first level exception condition. A second set of registers continuously tracks the instruction in tandem with the first set of registers, but is updatable during the processing of first level exception conditions by the exception handles. A monitor processes second level exception conditions occurring in the exception handler and precludes the second set of registers from being updated when it processes the second level exception conditions to permit the exception handler to restart from the point of the occurrence of a second level exception condition.

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J. A. Smith, et al., Implementing Precise Interrupts In Pipelined Processors, IEEE Transactions On Computers, 37:562-573 (1988).
C. Melear, The Design of the 88000 RISC Family, IEEE Micro, 9:26-38 (1989).

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