Exception handling method and system

Data processing: software development – installation – and managem – Software program development tool – Translation of code

Reexamination Certificate

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Details

C717S150000, C717S153000

Reexamination Certificate

active

06484314

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to a method and a system for increasing the speed of exception handling, in particular, to a method and a system for minimizing the number of instructions required for exception check handling, and to a medium for storing a program therefor.
2. Prior Art
In order to ensure, in a language processing system, the safety of a program written by a user, the detection of exceptions in a program written in a conventional language must be performed frequently so as to determine whether illegal pointer accesses have occurred or whether an index array is within a correct range. For example, in Java (trademark of Sun Microsystems, Inc.), when the following conditions are not satisfied, exceptions of types corresponding to individual conditions occur in order to ensure the safety of a program:
When the field of an object is to be accessed, the address of the object is not null.
When an element of an array is to be accessed, the address of the array is not null, and the index of the array falls within a correct range.
A divisor for the division of an integer is not 0.
In the C, C++ and FORTRAN languages, exception checks are not performed at the time of execution. In order to increase the speed of a program, such as a Java program frequently performing exception checking, the overhead required for exception checking must be minimized. In a compiler, even a reduction involving only one instruction can contribute greatly to an increase in the execution speed.
Conventionally, and mainly in the following two cases is processing performed when it is determined during the execution of a program that a condition exists for which an exception handling is required, and when an exception has occurred.
When a branching destination can be freely set (When both a comparison instruction and a branching instruction are employed).
When a branching destination used in common is set (an instruction is employed for branching, in a specific condition, to a handler prepared by an OS).
The outlines of the processing performed in these two cases will now be described.
<Case Wherein a Destination of a Branching Instruction can be Freely Set>
A jump destination (ERROR_HANDLING
1
,
2
) for each exception condition is prepared for the code to examine an exception condition while an operation is being executed. When an exception condition is established, the code at the jump destination is executed. Pseudo-code for the operation is shown below.
Check for exception condition 1
When condition 1 is established, jump to ERROR_HANDLING
1
.
. . .
. . .
Check for exception condition 2
When condition 2 is established, jump to ERROR_HANDLING
2
.
. . .
ERROR_HANDLING:
Set exception type
1
.
Jump to an exception handler.
ERROR_HANDLING
2
:
Set exception type
2
.
Jump to an exception handler.
In the above code, it is assumed that the underlined instructions are processes that are not required for normal processing during which no exceptions occur. If in response to the occurrence of an exception a comparison instruction or a branching instruction can be used to indicate the type of exception, program control can branch directly to an exception handler without any unnecessary branching being performed.
<Case where a jump destination of a branching instruction is used in common>
Pseudo-code for a condition wherein a jump destination of a branching instruction is used in common is shown below.
Set exception type
1
.
Check for exception condition 1.
When exception condition 1 is established, jump to ERROR_HANDLING.
. . .
. . .
Set exception type
2
.
Check for exception condition 2.
When exception condition 2 is established, jump to ERROR_HANDLING.
ERROR_HANDLING:
Obtain an exception type.
In the above code, it is assumed that the underlined instructions are processes that are not required for normal processing during which no exceptions occur. If a comparison instruction or a branching instruction can be used to indicate the type of exception, the execution of unnecessary instructions can be avoided when no exception occurs.
It is, therefore, an object of the present invention to provide a method and a system for generating an exception handling instruction and for avoiding the execution of unnecessary instructions.
It is also an object of the present invention to provide a method and a system for generating exception handling instructions without generating an instruction for substituting into a register a label indicating a type of exception.
It is another object of the present invention to provide a method and a system for generating an exception handling instruction by employing a comparison instruction or a branching instruction indicating the type of exception.
It is an additional object of the present invention to provide a method and a system for generating an exception handling instruction by employing an instruction for checking an exception and for branching to an exception handler.
It is a further object of the present invention to provide a method and a system for generating an exception handling instruction and for generating code having a small size.
It is one further object of the present invention to provide, in accordance with the contents of the memory at an address whereat the processing branches to an exception handler, an exception handling method and system for determining the type of exception that has occurred.
It is yet one more object of the present invention to provide, in accordance with the contents of the memory before and after an address whereat the processing branches to an exception handler, an exception handling method and system for determining the type of exception that has occurred.
SUMMARY OF THE INVENTION
To achieve the above objects, first, internal opcode in a compiler is read and one internal opcode is obtained. Whether or not the obtained internal opcode is an instruction for which exception checking is required is determined. If exception checking is required for the opcode, an exception checking instruction having a sequence of bits that are uniquely determined must be generated in accordance with the type of exception, without generating an instruction for substituting into a register a label indicating the type of exception. Then, a processor instruction is generated corresponding to the obtained internal opcode. The above processing is repeated for the remaining internal opcode, and an exception handling instruction is generated. An exception checking instruction is an instruction for checking whether an exception condition is established, and for branching to an exception handler when the exception condition is established.
At the step for the execution of a exception handling, when an exception occurs, an address is obtained whereat program control branches to the exception handler, and the contents of the memory at the address are read. The type of exception that has occurred is determined in accordance with the contents of the memory (bit pattern), and then an exception handling is performed in accordance with the type of exception that has been determined. The contents of the memory equivalent to or greater than one instruction may be read from the obtained address and its preceding and succeeding addresses.
Specifically in order to minimize the overhead of the exception handling in a sequence of instructions to be executed, an exception checking instruction is so generated that an instruction which is to be inserted into the code portion for normal operation is minimized to check whether the exception occurs. When an exception occurs, the pertinent address is obtained during an exception handling routine, and a sequence of instructions at the preceding and succeeding addresses are decoded. The decoded instructions are employed to determine the type of exception that has occurred.


REFERENCES:
patent: 4875160 (1989-10-01), Brown, III
patent: 5197138 (1993-03-01), Hobbs et al.
patent: 5481719 (1996-01-01), Ackerman et al.
patent: 5606696 (1997-02-01), Ackerman et al.
patent:

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