Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
1999-11-09
2004-02-17
Malzahn, David H. (Department: 2124)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C714S808000
Reexamination Certificate
active
06694344
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates in general to the monitoring of computer data. In particular, it relates to such monitoring in the conversion of data into other formats.
BACKGROUND OF THE INVENTION
Computer systems are largely constructed so that they comprise a large number of hardware registers, which serve as data sources or data targets. These registers can contain interrupts, addresses, control bits, status information, numerical data and the like for different parts of the computer. Numerical data are represented by sequences of binary digits or bits. The data bits in these binary bit sequences are in general divided into groups, each of 8 bits, each of these groups being known as a “byte”. In order to be able recognise the appearance of faulty data, a so-called “parity check bit” is assigned to each of these bytes at various stages of the passage of the data through the computer. In the case of the application of so-called “odd parity checking” the value of the parity bits is set so that the total 9-bit combination of the 8 data bits and the parity check bit produces an odd number of binary bits of the value 1, while with “even parity checking”, an even number results. Parity checks are carried out at different locations of the computer by determining the corresponding number of bits of the value 1 in each 9-bit combination. If “odd parity checking” is used and an even number of bits of value 1 is detected, it is then clear that this data segment contains an error. This is also valid if “even parity checking” is used and an odd number of bits of the value 1 is detected.
Such parity checking can also be employed in cases in which computer data is to be converted from one format to another, for example, from a decimal to a binary format or vice versa. With complicated conversions of computer data it is often very difficult to monitor the correct execution of this conversion or the functionality of the conversion logic during operation, since the monitoring logic which is conventionally used for computer data with the aid of parity bits and parity checkers in many cases prevents the data conversion, since the cost of parity calculation and checking for this would be unacceptably high and also prone to error.
One common method for monitoring is therefore in many cases to double the whole of the monitoring logic with a subsequent comparison of the results. Although such a solution is relatively simple to implement in terms of hardware, it naturally necessitates an immense hardware cost. Consequently, this “overhead” of about 110% generally cannot be tolerated; usually only 20 to 30% is allowed as an “overhead” for checking, for example, in very large systems.
It is therefore an object of the present invention to provide a method with the aid of which it is possible in a simple manner to monitor the conversion of computer data from one format to another format.
It is a further object of the present invention to provide such a method which is effective without a doubling of the corresponding hardware.
SUMMARY OF THE INVENTION
This and other objects are achieved by the present invention wherein the modulo residues (or remainders) of the numerical values in a first format are calculated prior to converting the numerical values into a second format. The residue values are stored while the numerical values are converted from the first format into a plurality of numerical values in a second format. Thereafter, the modulo residues are calculated for each of the plurality of numerical values in the second format. The first and second modulo residues are compared for each numerical value. If the first and second modulo residues are the same, then it is concluded that the conversion was error-free.
REFERENCES:
patent: 2919854 (1960-01-01), Singman
patent: 3124783 (1964-03-01), Adams
patent: 3624373 (1971-11-01), Birchall
patent: 3814923 (1974-06-01), Wang
patent: 3816728 (1974-06-01), Chen et al.
Gerwig Guenter
Haess Juergen
Kroener Michael
Pfeffer Erwin
Dougherty Anne V.
International Business Machines - Corporation
Malzahn David H.
Zarick Gail H.
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