Boots – shoes – and leggings
Patent
1985-10-17
1988-03-15
Zache, Raulfe B.
Boots, shoes, and leggings
G06F 1212
Patent
active
047317396
ABSTRACT:
A memory apparatus which includes an intermediate store addressed by logical addresses and a main store addressed by system addresses. The memory unit has a translator for translating logical addresses to system addresses. The translator includes a translation lookaside buffer having a system address store with first and second fields storing system addresses corresponding to each translated logical address and a control field including a flipper bit for indicating which one of the system addresses is the currently active real address. The control field also includes an eviction pending bit for each system address field. When the TLB is updated with a new translation, the previos active address field is marked with an eviction pending bit and the the previos inactive address field is written over with the new translation and marked active. After eviction from the intermediate store of data relying on the system address marked eviction pending, the eviction pending bit is turned off, freeing the space for subsequent new translations.
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Hanson Donald L.
Woffinden Gary A.
Amdahl Corporation
Munteanu Florin
Zache Raulfe B.
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