Event tagging time delay

Details Event tagging time delay Event tagging time delay

1990-02-16

1991-07-16

Heyman, John S.

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Comparing counts

377 26, 377 43, 328 55, 307603, H03K 5135, H03K 2100

Patent

active

050330667

ABSTRACT:
A time delay circuit for providing a delayed replica of a digital input signal including first and second counters for providing first and second count outputs offset relative to each other by a predetermined value indicative of a predetermined delay, and further including a first-in first-out (FIFO) memory for controllably storing selected values of the digital input signal together with corresponding first count output values. First comparison circuitry compares each digital input with the immediately prior digital input, and controls the FIFO memory to store (a) each digital input which is different from the immediately prior digital input, and (b) the first counter output value associated therewith. The FIFO memory circuit provides an output comprising (1) a digital output that corresponds to the earliest changed digital output which has not yet been utilized in the delayed replica of the digital input signal, and (2) a FIFO count output that corresponds to the first counter output value associated with such digital output. Second comparison circuitry responsive to the second counter output and the FIFO count output controls the FIFO memory circuit to change its output when the second counter output and the FIFO count output are equal.

REFERENCES:
patent: 3833854 (1974-09-01), Schonover
patent: 4290022 (1981-09-01), Puckette
patent: 4468796 (1984-08-01), Suga
patent: 4517684 (1985-05-01), Fennel
patent: 4809221 (1989-02-01), Magliocco et al.
patent: 4870665 (1989-09-01), Vaughn

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