Event driven programmer logic controller processor arrangement w

Details Event driven programmer logic controller processor arrangement w Event driven programmer logic controller processor arrangement w

1995-08-14

1998-06-23

Kim, Kenneth S.

Boots, shoes, and leggings

364140, 364579, 395250, 395736, G06F 1900

Patent

active

057713740

ABSTRACT:
A processor arrangement is described having a programmer logic controller (PLC) operating to a ladder diagram process. A number of event inputs (11-15) are provided connected to an interrupt buffer (31), in turn connected to a real time clock (32), for recording times of events of signals received on the event inputs and generating interrupts. Sequential storage locations in a cyclical buffer (60) store interrupts and their event times, where events occurring within a predetermined incremental time window are stored, with their event times, in a storage location for that time window. Each location of the cyclical buffer is inspected in sequence upon each new step of the sequential process. The PLC is arranged to operate on any events stored in the buffer which are affected by the new step of the sequential process before proceeding to the next step of the sequential process.

REFERENCES:
patent: 4941081 (1990-07-01), Kumar et al.
patent: 4975865 (1990-12-01), Carnette et al.
patent: 5072356 (1991-12-01), Watt et al.
patent: 5325522 (1994-06-01), Vaughn
patent: 5426774 (1995-06-01), Banerjee et al.

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