Event-controlled LCC stimulation

Details Event-controlled LCC stimulation Event-controlled LCC stimulation

1989-07-18

1991-11-26

Lall, Parshotam S.

Boots, shoes, and leggings

364488, 395500, G06F 1518

Patent

active

050688120

ABSTRACT:
A method for simulating a levelized logic circuit including an event-controlled feature for marking components to be reevaluated. An evaluation list is formed which lists signals and corresponding components of the logic circuit which are to be reevaluated. A second list is formed of each component and its corresponding output signals. The external input signals are also listed. Each external input signal is tested for change from a previous evaluation and, if so, the corresponding components in the re-evaluation list are marked for reevaluation. Each component, in levelized order, is then tested to determine whether that component is marked for re-evaluation and, if so, that component is re-evaluated and unmarked, and each signal in the component output signal list which has a non-empty re-evaluation list is tested to determine if the value of the signal has changed since the previous evaluation and, if so, all of the components in that signal's reevaluation list are marked for re-evaluation. Evaluation marks are stored as a marking bit in a memory location associated with a component. The components associated with frequently changing input signals are evaluated without setting or testing their evaluation marks. All reevaluation marks are cleared at the beginning of the execution of the simulation.

REFERENCES:
patent: 4775950 (1988-10-01), Terada et al.
patent: 4815024 (1989-03-01), Lewis
patent: 4866663 (1989-09-01), Griffin
patent: 4924429 (1990-05-01), Kurashita et al.
patent: 4945503 (1990-07-01), Takasaki
patent: 4965743 (1990-10-01), Malin et al.
Zeev Barzilai et al.; "HSS-A High Speed Simulator", IEEE Transactions of Computer-Aided Design; July, 1987, pp. 601-617.

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