Event-based temporal logic

Data processing: structural design – modeling – simulation – and em – Modeling by mathematical expression

Reexamination Certificate

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C703S014000, C703S015000, C716S030000, C716S030000

Reexamination Certificate

active

07433808

ABSTRACT:
In an embodiment, a computer-implemented method for modeling a system using a finite state machine representation is presented. An event-driven temporal logic operator may be associated with a first, active state in the finite state machine representation. A value of the temporal logic operator may be determined by a number of occurrences of an event during an existing activation of the first state associated with the temporal logic operator. A state transition from the first state to a second state may be executed based on the value of the temporal logic operator. The second state may be set as the active state.

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