Event-based temporal logic

Data processing: structural design – modeling – simulation – and em – Modeling by mathematical expression

Reexamination Certificate

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C703S015000, C703S016000, C703S017000

Reexamination Certificate

active

07941303

ABSTRACT:
A method for modeling a system as a finite state machine in a modeling environment is discussed. Embodiments receive a representation of a finite state machine model and provide an interface for incorporating a temporal operator into the finite state machine model. The temporal operator may be a Boolean function that includes at least one event parameter and defines a temporal logic condition. Embodiments may also receive a definition of a first temporal operator that defines a logic condition related to a number of occurrences of two or more different base events.

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Kalita et al., “SF2STeP: A CAD Tool for Formal Verification of Timed Stateflow Diagrams”, IEEE International Symposium on Computer-Aided Control System Design, CACSD 2000, Sep. 2000, pp. 156-162.

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