Evenly distributed RC delay word line decoding and mapping

Details Evenly distributed RC delay word line decoding and mapping Evenly distributed RC delay word line decoding and mapping

1996-12-02

1998-07-21

Nelms, David C.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36523001, G11C 800

Patent

active

057843309

ABSTRACT:
A device for accessing a specific word line in a memory array has improved noise protection by smoothing out the RC load in the word line mapping circuit. The word lines are respectively connected to rows of memory cells in the memory array, and predecoded word lines are used to decode encoded addresses which correspond to the various rows. The circuit connects the word lines to the predecoded word lines by gates which are tapped into the predecoded word lines, and the taps on a given predecoded word line are non-adjacent, to more evenly distribute the RC delay for each predecoded word line. In other words, the word lines are interspersed, out of order. The word lines can be interspersed randomly, or according to a predetermined function, such as a modulo function. The RC load for a given predecoded word line is preferably uniformly distributed along substantially the entire length of the predecoded word line.

REFERENCES:
patent: 4985865 (1991-01-01), Houston
patent: 5128897 (1992-07-01), McClure
patent: 5323360 (1994-06-01), Pelley, III
patent: 5381377 (1995-01-01), Bewick et al.
patent: 5414663 (1995-05-01), Komarek et al.
patent: 5546350 (1996-08-01), Gillingham
patent: 5577003 (1996-11-01), Fuji

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