Even bus clock circuit

Details Even bus clock circuit Even bus clock circuit

1997-09-26

1999-04-27

Nelms, David

Static information storage and retrieval

Addressing

Sync/clocking

365194, 327145, 327218, 395551, G11C 800

Patent

active

058986405

ABSTRACT:
An even bus clock circuit generates logic pulses in response to substantially coincident rising edges of a processor clock and a bus clock over a given range of processor clock to bus clock ratios that includes whole integers and half integers. The even bus clock circuit includes a delay element for receiving the bus clock and generating a delayed bus clock, a first flip-flop for receiving the processor clock at a data input and receiving the delayed bus clock at a clock input, and a second flip-flop for receiving a data output of the first flip-flop at a data input, receiving the processor clock at a clock input and generating a data output that is coupled to an asynchronous reset input of the first flip-flop. The logic pulses are generated at the data output of the first flip-flop and have a pulse width of substantially the same duration as a single cycle of the processor clock.

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H. Taub and D. Schilling, Digital Integrated Electronics, Chapter 10, pp. 322-355 (1977).

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