Coating processes – Electrical product produced – Integrated circuit – printed circuit – or circuit board
Patent
1985-06-21
1987-06-02
Smith, John D.
Coating processes
Electrical product produced
Integrated circuit, printed circuit, or circuit board
427 99, 430312, H01L 2188, H01L 21312
Patent
active
046702970
ABSTRACT:
A first masking layer of a first resist is provided over a semiconductor substrate and is patterned in a selected region to provide a masked region over which an airbridge interconnect will be provided. A second relatively thick layer of a second, different type of resist and a third relatively thin layer of resist are provided, respectively, over the substrate. The second and third layers of resist are patterned to provide an aperture having overhanging portions exposing the previously applied patterned regions of the first layer, and selected adjacent portions of the substrate. The second and third layers may also be patterned to provide a region for a patterned strip conductor. A stream of evaporated metal is directed towards the substrate and deposited within the apertures to provide an airbridge interconnect conductor and patterned strip conductor. The overhanging portions of the apertures provide separation between the metal layer deposited within the aperture and the metal layer deposited over the third masking layer, allowing the second and third masking layers to be lifted-off without disturbing the conductors. The masked regions underlying the bridges are also removed leaving the airbridge interconnect and patterned strip conductor.
REFERENCES:
patent: 4054484 (1977-10-01), Lesh
patent: 4200975 (1980-05-01), Debiec
patent: 4289846 (1981-09-01), Parks
patent: 4436766 (1984-03-01), Williams
patent: 4526859 (1985-07-01), Christensen
patent: 4533624 (1985-08-01), Sheppard
patent: 4536421 (1985-08-01), Matsuzawa
patent: 4567132 (1986-01-01), Fredericks
patent: 4568411 (1986-02-01), Martin
"Portable Conformable Mask-A Hybrid Near-Ultraviolet and Deep-Ultraviolet Patterning Technique" by B. J. Lin, SPIE vol. 174 Developments in Semiconductor Microlithography IV (1979), pp. 114-121.
Patent application Ser. No. 388,841, filed Jun. 16, 1982, inventor Walter Fabian, assigned to Raytheon Company, to be issued into U.S. Pat. No. 4,525,919 on Jul. 2, 1985.
Day John
Durschlag Mark S.
Lee Kyu-Woong
Maloney Denis G.
Raytheon Company
Sharkansky Richard M.
Smith John D.
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