Coded data generation or conversion – Converter calibration or testing
Reexamination Certificate
1998-10-30
2001-01-23
JeanPierre, Peguy (Department: 2819)
Coded data generation or conversion
Converter calibration or testing
C341S155000
Reexamination Certificate
active
06177894
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a performance evaluation system and method for evaluating the effective number of bits and the differential non-linearity of an analog-digital converter (ADC) which converts an analog signal into a digital signal and which is implemented by a single semiconductor integrated circuit or a combination of a plurality of semiconductor integrated circuits.
2. Description of the Related Art
An approach to evaluate ADC's is categorized into a static and a dynamic characteristic evaluation technique. According to the static characteristic evaluation technique, a precisely defined d.c. voltage is applied to an ADC, which is a device under test (DUT), and a response from the ADC is observed in order to estimate “a difference between the transition voltage of an actual ADC and the transition voltage of an ideal ADC” in a computer or like means based on the differential nonlinearity, hereafter referred to as DNL. The differential nonlinearity or DNL is obtained by the comparison of a difference in the upper limit amplitude of the analog signal (actual step size) as adjacent quantized codes are delivered from the ADC against an ideal step size which corresponds to 1 LSB, and enables a localized fault which depends on a particular code to be detected. Thus, DNL for ADC is defined as follows:
DNL=A
in
(
Q
m+1
)—
A
in
(
Q
m
)−1[
LSB]
(1)
where Q
m+1
and Q
m
are two adjacent quantized codes and A
in
(Q
n
) represents the upper limit of the amplitude of the analog signal which corresponds to a quantized code Q
n
. It is seen that DNL equals zero if “the difference between adjacent transition amplitudes” remains constant and equals the step size corresponding to 1 LSB. However, the static characteristic evaluation technique cannot determine the nonlinearity of an ADC under test which depends on the frequency of a signal being applied.
On the other hand, according to the dynamic characteristic evaluation technique, a periodic signal is applied to an ADC under test, a response from the ADC is observed, and “a difference between the transitional voltage of an actual ADC and the transition voltage of an ideal ADC” is; estimated as in a computer. This technique has an advantage that a characteristic which closely approximates an actual operation of the ADC, which is under test, can be estimated. Dynamic characteristic evaluation techniques which utilize a sine wave (sinusoidal wave) as an input signal include a histogram approach, an FFT approach and a curve fitting approach mentioned below.
(a) In the histogram approach, a sine wave signal from a sine wave generator
11
is applied to an ADC
14
under test, as shown in FIG.
1
A. Using a digital waveform which represents the response of the ADC, a histogram for respective codes is obtained by a histogram analyzer
17
. A DNL estimator
18
then determines a difference between the histogram for the actual ADC and the histogram of an ideal ADC, and divided by the histogram of the ideal ADC, thus estimating the DNL. The normalization of the difference in the histograms by the histogram of the ideal ADC accounts for a non-uniform distribution of the sine wave histogram. By way of example, the relative number of samples for an output from a 6 bits ADC will be as shown in
FIG. 1B
where the total number of samples is equal to 1024, and the resulting DNL will be obtained as shown in FIG.
1
C.
(b) In the FFT approach, a digital signal representing the response of the ADC
14
under test is Fourier transformed as by FFT (fast Fourier transform), and is separated in the frequency domain into a signal (namely, a frequency spectrum of the sine wave applied) and noises (namely, a spectrum of quantization noises or a sum of spectra other than the frequency of the sine wave applied), thus determining a signal-to-noise ratio (SNR).
Specifically, as shown in
FIG. 2A
, a sine wave signal from a sine wave generator
11
is passed through a low pass filter
12
to eliminate unwanted components therefrom before it is fed to a sample-and-hold circuit
13
where the sine wave signal is sampled periodically and held therein for feeding an ADC
14
under test. A response output from the ADC
14
is fed to an FFT unit
15
where it is transformed into a signal in the frequency domain, which is then fed to an SNR estimator
16
. On the basis of a result of the FFT as illustrated in
FIG. 2B
, the SNR estimator
16
determines the signal-to-noise ratio SNR by dividing the sine wave signal component G
SS
(f
0
) by the noise component &Sgr;
f
G
nn
(f) where f≠f
0
.
If the quantization noise increases in the ADC
14
for reason of fault, the signal-to-noise ratio SNR is degraded, increasing the number of bits among the total number of bits in the ADC
14
which are influenced by the quantization noise. It is then possible to estimate the effective number of bits (ENOB) of the tested ADC from the signal-to-noise ratio observed, and can be given by the equation (2) indicated below.
ENOB
=
SNR
[
dB
]
-
1.76
6.02
[
bits
]
(
2
)
By changing the frequency f
0
of the sine wave signal applied, the frequency dependency of ENOB can be determined.
(c) In the curve fitting approach with the sine wave, parameters (such as frequency, phase, amplitude, offset etc.) of an ideal sine wave are chosen so that the square error between a sampled digital signal and the ideal sine wave is minimized. An rms (root-mean-square) error determined in this manner is compared against the rms error of the ideal ADC having the same number of bits to estimate the effective number of bits.
Means for generating an analog signal such as a sine wave is described in detail in “Theory and Application of Digital signal Processing” by Lawrence R. Rabiner and Bernard Gold; Prentice-Hall, 1975, in particular, “9.12: Hardware realization of a Digital Frequency Synthe-sizer”, for example.
Problems with the use of conventional dynamic evaluation approach are discussed below.
(a) When the histogram approach is used to estimate the DNL of an ADC with a high precision, a very long time is needed for the determination. By way of example, an estimation of the DNL for an 8-bit ADC with a reliability of 99% and for an interval width of 0.01 bit requires 268,000 samples. For a 12-bit ADC, as many as 4,200,000 samples are required. (See, for example, Joey Doernberg, Hae-Seung Lee, David A. Hodges, 1984.) When the ADC under test exhibits a hysteresis, it is likely that any fault therein cannot be detected by using the histogram approach. Here it is assumed that when an input signal crosses a given level with a positive gradient, a corresponding code breadth is enlarged, increasing the number of observations, while when the input signal crosses the given level with a negative gradient, the corresponding code breadth shrinks, decreasing the number of observations. According to the histogram approach, no distinction is made in the direction in which the input signal changes, and accordingly, the number of observations for the positive gradient and the number of observations for the negative gradient are added together in the ultimate number of observations. Hence, an increase and a decrease in the number of observations cancel each other, and the code breadth will be one close to a code breadth for a fault-free ideal ADC. (See, for example, Ray K. Ushani, 1991.) As a consequence, the DNL which can be estimated with the histogram approach is a result of comparison of a difference in mean values of output code breadth against the ideal step size corresponding to 1 LSB. In addition, there must be a relationship other than an integral multiple between the frequency of the input sine wave and the sampling frequency of the ADC. (See, Joey Doernberg, Hae-Seung Lee, David A. Hodges 1984.)
With a histogram approach using the sine wave input, the estimated value of DNL remains little unchanged if the internal noise of the ADC is high or low. In other words, there remains a problem with a histogram a
Advantest Corporation
Gallagher & Lathrop
Jean-Pierre Peguy
Lane Timothy J.
LandOfFree
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