Evaluation method of a field effect transistor

Details Evaluation method of a field effect transistor Evaluation method of a field effect transistor

2006-06-13

2006-06-13

Abraham, Fetsum (Department: 2826)

Semiconductor device manufacturing: process

Including control responsive to sensed condition

Electrical characteristic sensed

C438S014000, C438S015000, C438S018000

Reexamination Certificate

active

07060511

ABSTRACT:
The present invention provides a method for estimating resistance value of an LDD region that works in an actual FET and forming an optimum LDD region. Therefore, the present invention provides an FET in which OFF (leakage) current is reduced and has superior switching characteristics. An equivalent circuit is assumed so as to estimate an external resistance value. The equivalent circuit is a circuit in which an external resistor is serially-connected to the drain side of a conventional FET. And the threshold voltage and the external drain voltage—drain current characteristics of the FET having an LDD structure are measured, and the result is applied to the equivalent circuit. Regarding an external drain voltage when drain current is saturated as an external saturation drain voltage, a saturation drain voltage in an imaginary FET taking off the external resistor from the estimating FET is obtained from the threshold voltage. The external resistance value is estimated from the external saturation drain voltage, the saturation drain current, and the saturation drain voltage.

REFERENCES:
Mitsumasa Koyanagi, “Submicron Device II, 4.4.3 Effective Channel Length and Series Resistance of LDD Structure,” Jan. 30, 1988, p. 202, line 14—p. 208, line 12.

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