Evaluation board and failure location detection method

Details Evaluation board and failure location detection method Evaluation board and failure location detection method

2011-04-12

2011-04-12

Patel, Paresh (Department: 2858)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

For fault location

C324S719000, C324S754220

Reexamination Certificate

active

07924022

ABSTRACT:
An evaluation board, on which is mounted a chip to be evaluated is provided. Particularly, the evaluation board includes a monitoring window for monitoring a power supply part, a ground part, and a surface of the chip, a first signal input part for inputting signals to the chip, and a second signal input part for inputting signals to the chip, wherein the second signal input part is placed as to sandwich said monitoring window between itself and the first signal input part.

REFERENCES:
patent: 5895967 (1999-04-01), Stearns et al.
patent: 6710459 (2004-03-01), Hsu
patent: 6740965 (2004-05-01), Hsu et al.
patent: 6784684 (2004-08-01), Tanimura
patent: 64-65860 (1989-03-01), None
patent: 11-111759 (1999-04-01), None

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