Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2002-09-26
2004-08-10
Decady, Albert (Department: 2133)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C438S633000, C451S056000
Reexamination Certificate
active
06774660
ABSTRACT:
The present application claims priority under 35 U.S.C. §119 to Japanese Application No.2000-288451, filed on Sep. 22, 2000, which is hereby incorporated by reference in its entirely for all purposes.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an evaluating pattern for measuring an erosion of a semiconductor wafer polished by a chemical mechanical polishing method.
2. Description of the Related Art
A chemical mechanical polishing method (CMP method) has bees used for forming a semiconductor device. As normally, a plurality of semiconductor devices are simultaneously formed on a semiconductor wafer, such CMP method is applied for the semiconductor wafer.
In the case where the CMP method is applied for a damascene process, occurrence of an erosion in a densely packed region where many contact holes or conductive lines are thick in a narrow distance. The erosion is that a thickness of an insulating region in the densely packed region becomes thin by the CMP method, compared with a predetermined thickness. The reason is reported that a speed of polishing the insulating layer becomes faster in the densely packed region.
If the thickness of the insulating layer becomes thinner beyond a permissible range by the erosion, it is possible that an insulation is broken or a current leak occurs in the semiconductor device.
The semiconductor wafer which includes such semiconductor device having such excessive erosion is evaluated as a defective product by measuring the thickness of the insulating layer. A contact type measure for measuring bumps occurred by the erosion is used for such measurement.
As the contact type measure directly contacts with elements in the semiconductor device, it is possible to damage the elements. As a result, such damage may decline a yield of the semiconductor device.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an evaluating pattern for measuring an erosion of a semiconductor wafer polished by a chemical mechanical polishing method.
To achieve the object, an evaluating pattern of one typical invention is comprised of a conductive pattern which has a rectangular configuration, an insulating layer which is formed on the conductive pattern, and a conductive material filled into contact holes which is formed in the insulating layer on the middle of the conductive pattern.
According to the present invention, it is easy to recognize the evaluation pattern on a semiconductor wafer. As a measuring point is arranged in the middle of the rectangular conductive pattern, it is facile to identify the measuring point. That is, the measuring point in the middle of the rectangular conductive pattern is easily identified by recognizing sides of the rectangular conductive pattern.
REFERENCES:
patent: 5723874 (1998-03-01), Baker et al.
patent: 5890951 (1999-04-01), Vu
patent: 6480017 (2002-11-01), Narita
patent: 2000-021882 (2000-01-01), None
patent: 2000-058611 (2000-02-01), None
De'cady Albert
Kerveros James C.
Oki Electric Industry Co. Ltd.
Volentine & Francos, PLLC
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