Ethernet switching architecture and dynamic memory...

Details Ethernet switching architecture and dynamic memory... Ethernet switching architecture and dynamic memory...

2006-08-08

2006-08-08

Pham, Chi (Department: 2616)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S474000

Reexamination Certificate

active

07088730

ABSTRACT:
This invention discloses a dynamic memory allocation method for an Ethernet switching architecture, which can resolve problems with the limitations of transmission bandwidths and transmission port counts in a conventional network packet switching. The method comprises steps of providing a plurality of input ports and output ports, providing a shared memory for storing packet segments of a plurality of packets, providing a first link RAM (Random Access Memory) for controlling a making and reading of a single linked list for the packet segments of each the plurality of packets, and providing a second link RAM serving as a FIFO (first in first out) device for co-managing an obtaining of the link address spaces at the corresponding input ports before the single linked list been made, and a releasing of the link address spaces at the corresponding output ports after the single linked list been read.

REFERENCES:
patent: 6456590 (2002-09-01), Ren et al.

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