Ethernet switch with a share memory structure and method for...

Multiplex communications – Pathfinding or routing – Through a circuit switch

Reexamination Certificate

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C370S352000

Reexamination Certificate

active

06577625

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial No. 87109990, filed Jun. 22, 1998, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to an Ethernet element, and more particularly to an Ethernet switch.
2. Description of Related Art
Currently, Ethernet, a most common Local Area Network (LAN), has been used in information communication network market. In early time, the structure of Ethernet was implemented by means of 10BASE5, called a Bus Topology Network. Furthermore, 10BASE2 is a cost-saving and revised form of the 10BASE5.
Although the 10BASE2 is also a Bus Topology Network and operates at a frequency of 10 MHz, a coaxial cable used has different properties and the maximum of transmission length is limited to less than 200 m. There are many disadvantages exiting in the structure of the 10BASE5 or 10BASE2. For example, cost for installing is higher; the installing for the 10BASE5 or 10BASE2 network is inflexible; and distribution line systems in buildings can not be effectively used. To solve the disadvantages mentioned above, 10BASE-T, a Star Topology Network system established by use of twin-stranded wires, is used.
The larger the structure of Local Area Network is, the more the amount of transmitting on the Local Area Network will be. When the number of nodes for connections on the Local Area Network is increased, the efficiency of the Ethernet is decreased. In order to satisfy the requirements of the large structure of the Local Area Network or high-speed data terminal equipment, a high-speed Ethernet operating at a higher frequency is provided. The high-speed Ethernet which operates at a frequency of 00 MHz, further enhances the functions of the Ethernet network 10BASE. In the high-speed Ethernet, a media independent interface (MII) is defined. Therefore, the high-speed Ethernet can be connected to another network, such as 100BASE-TX, 100BASE-T4 or 100BASE-FX, by using twin-stranded wires or fiber optical cables via network nodes.
Basically, the 10BASE5, 10BASE2, 10BASE-T, 100Base-TX, 100BASE-T4 or 100BASE-FX is a sharing bandwidth network system. All connected nodes on the network system can share the bandwidth thereof. The bandwidth of the network system 10BASE is 10 MHz while the bandwidth of the 100BASE is 100 MHz. When the number of the nodes connected is over a threshold value, the performance of the sharing network system reaches a best condition. A segmenting methodology, different from the method of accelerating operating pulse frequency, is used to improve the functions of the Ethernet system. The segmenting methodology segments the entire network system into several separated sub-networks. Each separated sub-network is located within a different range of collision domain. Nodes connected to different sub-networks are unable to share the bandwidths of the sub-networks with each other. If the network system is not segmented, each node of the Local Area Network 100BASE having 100 share nodes can share a bandwidth of 1 MHz only. However, if the system having 100 nodes is divided into 2 segments, each node of the Local Area Network 100BASE can share a bandwidth of 2 MHz. A segmented Local Area Network system having an Ethernet protocol is also called a switched Ethernet. Packets transmitted between the two segments of the network system are switched by use of an Ethernet switch. The Ethernet switch is used to switch packets between different segments of the local Area Network system. Packets transmitted from one segment to another segment is forwarded, but packets in the same segment transmitted from one node to another node will not be switched. These prior arts all are disclosed in U.S. Pat. No. 5,274,631, 5,491,694 and 5,588,151.
FIG. 1
is a circuit block diagram showing an Ethernet switch having a distribution memory structure according to the prior art.
Referring to
FIG. 1
, the prior Ethernet switch includes at least a switching IC
10
and a plurality of port ICs
11
a
,
11
b
and
11
c
. The switching IC
10
is used for data switching and transmitting control of each port. Each port IC has a memory. For example, the IC port
11
a
has a built-in memory
12
a
which is used to store and switch packet data. In the structure of the switch, when network data are transmitted from a port
13
a
to a port
13
c
, the data must be first stored in the memory
12
a
and then stored in a memory
12
c
. As shown in
FIG. 1
, the size of the memory of each port IC must have been previously decided when designed. Since any port of the network switch is likely connected to a Local Area Network, such as 10BASE5, 10BASE2, 10BASE-T, 100BASE-TX, 100BASE-T4 or 100BASE-FX, with a different specification, each port IC should be given a larger storage capacitance of memory for being suitable for different specifications. Therefore, more memory consumption is caused. Furthermore, data transmission must be implemented through two memories, such that the efficiency of the network switch is decreased.
SUMMARY OF THE INVENTION
In view of the above, the first object of the invention is to disclose a function of connecting a network system 10BASE to a network system 100BASE, thereby extending the uses of the old system to new system.
The second object of the invention is to disclose an Ethernet switch having a share memory structure for saving required memories of the switch.
In addition, the third object of the invention is to disclose a method for accomplishing the functions, of the switch. The method includes: sharing memory; storing a packet buffer pool; handling packet buffer pool congestion; and switching network packets.
According to the invention, the Ethernet switch having a share memory structure is provided for selectively transmitting network packets. The switch includes: a memory device, a memory controller, a data switching controller and more than two network ports. Furthermore, the memory device provides network packet accesses and stores routing data. The memory controller is coupled to the memory device for managing/controlling network packets in the memory device. The data switching controller is coupled to the memory controller for packet routing/learning. Each network port is coupled to the memory controller and data switching controller. The Ethernet switch of the invention has an advantage of saving required memories thereof.
The main object of the invention is to provide an Ethernet switch having a share memory structure for selectively transmitting network packets. The switch includes: a routing table; a packet buffer; a share memory access controller; a data switching controller; more than two network ports; and a buffers manager. Moreover, the share memory access controller coupled to the routing table and the packet buffer consists of a means for arbitrating, a means for data multiplexing, a means for addressing, and a means for access command controlling. The data switching controller coupled to the share memory access controller consists of a means for initializing, a means for arbitrating and a means for aging the routing table, and network routing/learning. Each network port is coupled to the share memory access controller and the data switching controller. The buffer manager is coupled to each network port. The buffer table is coupled to the buffer manager. The routing table is used to store routing data of packets by means of the share memory access controller. The packet buffer accepts packet accesses requested by each network port by use of the share memory access controller. The buffer table records the use statuses of the packet buffer by means of each network port and the share memory access controller. The buffer manager learns the use statuses of packet buffer in virtue of each network port and the share memory access controller, thereby managing the packet buffer.
According to a preferred embodiment of the invention, a memory device includes a routing table and a packet buffer. The rou

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