Ethernet packet header cache

Details Ethernet packet header cache Ethernet packet header cache

2005-09-20

2005-09-20

Kim, Hong (Department: 2186)

Electrical computers and digital processing systems: multicomput

Multicomputer data transferring via shared memory

C709S218000, C709S238000, C711S120000

Reexamination Certificate

active

06947971

ABSTRACT:
Methods and apparatus for caching information associated with packets are disclosed. According to one aspect of the present invention, a system for processing a packet includes a controller with a processor and a controller data cache, a bus, a memory interface, and a separate data cache. The memory interface may be accessed by the controller via the bus, and is arranged to be in communication with a substantially external memory. The separate data cache, which is also in communication with the controller via the bus, caches information associated with the packet such that the controller accesses the separate data cache to obtain the information associated with the packet when the controller needs to decide how to process the packet.

REFERENCES:
patent: 6018763 (2000-01-01), Hughes et al.
patent: 6076147 (2000-06-01), Lynch et al.
patent: 6427170 (2002-07-01), Sitaraman et al.
patent: 6751704 (2004-06-01), Ng
patent: 2002/0174252 (2002-11-01), Hayter et al.
Jim Handy, The Cache Memory Book, Academic Press, Inc., 1993, pp 62-65.

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