Semiconductor device manufacturing: process – Chemical etching – Liquid phase etching
Reexamination Certificate
2002-03-05
2004-09-14
Zerneke, David A. (Department: 2829)
Semiconductor device manufacturing: process
Chemical etching
Liquid phase etching
C438S396000, C438S650000, C438S669000, C438S691000, C438S692000, C438S693000, C438S697000, C438S704000, C438S722000, C438S689000, C438S745000, C438S748000, C216S006000, C216S016000, C216S017000, C216S100000, C216S108000, C216S109000
Reexamination Certificate
active
06790786
ABSTRACT:
TECHNICAL FIELD
This invention relates to semiconductor processing methods, and to methods of forming capacitors.
BACKGROUND OF THE INVENTION
One common goal in capacitor fabrication is to maximize the capacitance for a given size capacitor. It is desirable that stored charge be at a maximum immediately at the physical interface between the respective electrodes or capacitor plates and the capacitor dielectric material between the plates. Many integrated circuitry capacitors have electrodes or plates which are formed from doped semiconductive material such as polysilicon. The polysilicon is usually heavily doped to impart a desired degree of conductivity for satisfactory capacitor plate operation.
One drawback of heavily doping polysilicon is that during operation a charge depletion region develops at the interface where charge maximization is desired. Hence, a desired level of charge storage is achieved at a location which is displaced from the interface between the capacitor plate and the dielectric material. Another drawback of heavily doped polysilicon capacitor plates is that during processing, some of the dopant can migrate away from the polysilicon and into other substrate structures. Dopant migration can adversely affect the performance of such structures. For example, one type of integrated circuitry which utilizes capacitors are memory cells, and more particularly dynamic random access memory (DRAM) devices. Migratory dopants from doped polysilicon capacitor plates can adversely impact adjacent access transistors by undesirably adjusting the threshold voltages.
As the memory cell density of DRAMs increases there is a continuous challenge to maintain sufficiently high storage capacitance despite decreasing cell area. Additionally there is a continuing goal to further decrease cell area. The principal way of increasing cell capacitance heretofore has been through cell structure techniques. Such techniques include three dimensional cell capacitors such as trench or stacked capacitors.
Highly integrated memory devices, such as 256 Mbit DRAMs and beyond, are expected to require a very thin dielectric film for the 3-dimensional capacitor of cylindrically stacked or trench structures. To meet this requirement, the capacitor dielectric film thickness will be below 2.5 nm of SiO
2
equivalent thickness. Insulating inorganic metal oxide materials, such as Ta
2
O
5
and barium strontium titanate, have high dielectric constants and low leakage current which make them attractive as cell dielectric materials for high density DRAMs and non-volatile memories. All of these materials incorporate oxygen and are otherwise exposed to oxygen and anneal for densification to produce the desired capacitor dielectric layer.
In many of such applications, it will be highly desirable to utilize metal for the capacitor electrodes, thus forming a metal-insulator-metal capacitor. In other applications, it may still be desirable to use polysilicon as part of the capacitor electrode material using a conductive or other diffusion barrier, such as platinum, to avoid formation of insulative oxides of the electrode material. Certain metal materials such as platinum are, however, extremely challenging to remove by chemical etching, or by chemical-mechanical polishing processes. It would therefore be desirable to provide improved methods of etching these materials.
While the invention was motivated from this perspective, it is in no way so limited to addressing or overcoming any aspect of this particular problem, however. The invention is seen to have applicability to any method of processing particular metal comprising layers utilizing any integrated circuitry construction. The invention is only limited by the accompanying claims appropriately interpreted in accordance with the doctrine of equivalents without limiting reference to the specification, with the specification herein only providing but exemplary preferred embodiments.
SUMMARY
The invention includes semiconductor processing methods, including methods of forming capacitors. In one implementation, a semiconductor processing method includes providing a semiconductor substrate comprising a layer comprising at least one metal in elemental or metal alloy. The metal comprises an element selected from the group consisting of platinum, ruthenium, rhodium, palladium, iridium, and mixtures thereof. At least a portion of the layer is etched in a halogenide, ozone and H
2
O comprising ambient.
In one implementation, a semiconductor processing method includes forming a layer comprising at least one metal in elemental or metal alloy form over at least one side of a semiconductor wafer. The metal comprises an element selected from the group consisting of platinum, ruthenium, rhodium, palladium, iridium, and mixtures thereof. The wafer has a central portion surrounded by a peripheral portion. Masking material is formed over the central portion of the layer while the peripheral portion is left outwardly exposed. The peripheral exposed portion of the layer is etched from the wafer using a halogenide, ozone and H
2
O comprising ambient while the masking material is received over the central portion.
In one implementation, a method of forming a capacitor includes forming first and second capacitor electrode layers separated by a capacitor dielectric region over a substrate. At least one of the capacitor electrode layers comprises at least one metal in elemental or metal alloy form, the metal comprising an element selected from the group consisting of platinum, ruthenium, rhodium, palladium, iridium, and mixtures thereof. Masking material is formed over a first portion of said at least one capacitor electrode layer while leaving a second portion of said at least one capacitor electrode layer exposed. The exposed second portion of said at least one capacitor electrode layer is etched using a halogenide, ozone and H
2
O comprising ambient while the masking material is received over the first portion effective to form a desired pattern of said at least one capacitor electrode layer.
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patent: 4039698 (1977-08-01), Fraser et al.
patent: 6144871 (2000-11-01), Saito et al.
patent: 6290736 (2001-09-01), Evans
patent: 4333935 (1995-04-01), None
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patent: 08-153707 (1996-06-01), None
patent: 2001-240985 (2001-09-01), None
Flynn Patrick M.
Fucsko Janos
Morgan Paul A.
Kilday Lisa
Zerneke David A.
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