Etching process using a buffer layer

Details Etching process using a buffer layer Etching process using a buffer layer

2000-06-20

2001-02-20

Powell, William (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S719000, C438S721000, C438S756000

Reexamination Certificate

active

06191047

ABSTRACT:

BACKGROUND OF THE INVENTION
The Field of the Invention
The present invention involves etching processes in microelectronics technology. More particularly, the present invention involves methods of ameliorating etch rate uniformity problems in batch fabrication operations by providing a buffer layer to be etched on each semiconductor substrate in the batch. The present invention also ameliorates destructive etching into otherwise etch-selective structures on a semiconductor substrate due to unwanted prolonged etching into neighboring structures. In particular, the present invention involves use of an electrically conductive buffer layer on a semiconductor substrate that etches faster than other layers and surfaces incident to forming a cavity.
The Relevant Technology
In the context of this document, the term “semiconductor substrate” is defined to mean any construction comprising semiconductive material, including but not limited to bulk semiconductive material such as a semiconductive wafer, either alone or in assemblies comprising other materials thereon, and semiconductive material layers, either alone or in assemblies comprising other materials. The term “substrate” refers to any supporting structure including but not limited to the semiconductor substrates described above. A semiconductor device refers to a semiconductor substrate upon which at least one microelectronic device has been or is being batch fabricated. A buffer layer in etch processing is a layer of a material to which a specific etch is selective.
Uniformity across a semiconductor device is a concern to the process engineer during many process steps in the fabrication of microelectronic devices. One such process step is formation of cavities by etching in which an etch may leave some cavities incompletely etched and others overetched such that an underlying layer is not exposed or is damaged, respectively.
The problem of etch uniformity can be ameliorated by performing a planarization step before the etch. If a planarization step is not done, and the layer to be etched is uneven, an etch may penetrate the layer and contact the substrate in some places where the layer was over the substrate, and the etch may not contact the substrate in some places where the layer was thick. Such an etch uniformity problem is illustrated in FIG.
1
. In
FIG. 1
, which is a cross-sectional area, the exposing of a fragment of a semiconductor device
10
is illustrated wherein a substrate
12
has four gate stacks
14
built thereupon. Gate stacks
14
comprise a gate oxide layer (not shown), a polysilicon layer
16
, a silicide layer
18
, and an insulative nitride cap
20
. Insulative nitride spacers
22
protect gate stacks
14
. An insulative layer
26
covers gate stacks
14
and substrate
12
.
FIG. 1
illustrates one example of etch an uniformity problem in which the plane of an insulative layer upper surface
28
is not parallel to the plane of a substrate upper surface
30
. An etch of insulative layer
26
will lead to inconsistent etch depths. An etch cavity
32
fails to penetrate and thus fails to provide a completed cavity. An etch cavity
34
overexposes an active area or interconnect lower level and thus damages the underlying layer. In the case of
FIG. 1
, the underlying layer is substrate
12
.
Another problem of etch uniformity is an inadequately executed etch-selective process in which, although selective to structures that are to remain, a prolonged etch will nonetheless damage structures as illustrated in FIG.
2
. In
FIG. 2
, even if the topography of insulative layer
26
is planar, prominent structures on substrate
12
, such as gate stacks
14
, will be exposed to etching effects and detrimentally etched before substrate
12
is exposed.
What is needed is a method of etching a cavity that avoids the etch uniformity problems of the prior art.
SUMMARY OF THE INVENTION
The present invention is directed toward building a microelectronic device in which a semiconductor substrate uses an etch buffer layer in a processing method in which the buffer layer will act as an etch uniformity aid. The present invention is also directed toward an etch buffer layer that may have additional structural utility in the finished microelectronic device.
In one method of making the microelectronic device, a semiconductor substrate is covered with an etch buffer layer formed of a conductive material and with an insulative layer. A first etch is performed by patterning and etching through a mask. This first etch penetrates the insulative layer and forms a cavity. This first etch is selective to the buffer layer and leaves a first cavity that exposes the buffer layer.
A second etch is performed that is selective to the insulative layer and the semiconductor substrate while etching the buffer layer. The effect of the second etch is that the insulative layer is substantially undercut due to the etch of the buffer layer and due to selectivity to all other etch-exposed structures of the semiconductor substrate. The undercut leaves a laterally-oriented second cavity within which lateral surfaces of the buffer layer are exposed and which forms a space between the top of prominent semiconductor substrate features and the insulative layer.
Following the second etch, a method of covering the laterally exposed surfaces of the buffer layer exposed by the undercut is chosen in order to isolate the remaining laterally exposed surfaces of the buffer layer. Isolation is required when the buffer layer is electrically conductive and the first cavity is filled with an electrically conductive material such as an interconnect or bit line contact. One preferred method of covering the laterally exposed surfaces of the buffer layer is by partial reflow of the insulative layer. Partial reflow will cause materials above the undercut area to sag and close off the undercut. Partial reflow of the insulative layer can be accomplished by rapid thermal processing (RTP). Another preferred method of covering the laterally exposed surfaces of the buffer layer is by filling the undercut with another material. Filling the undercut with another material is accomplished by forming a liner layer that deposits within the first and the second cavities.
The buffer layer in a further embodiment is formed from an insulative material. One example of a suitable insulative material is oxide deposited by decomposition of tetraethyl orthosilicate (TEOS). Thus, for example, the buffer layer can be formed of TEOS, and the insulative layer formed of a material such as borophosphosilicate glass (BPSG). The first etching process is then preferably conducted as an anisotropic dry etch, and the second etching process is conducted with an etchant comprising tetramethyl ammonium hydroxide (TMAH) in an aqueous solution of dilute HF.
These and other features of the present invention will become more fully apparent from the following description and appended claims, or may be learned by the practice of the invention as set forth hereinafter.


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U. Schnakenberg et al., TMAHW Etchants for Silicon Micromachining, 91CH2817-5/91/000-0815, IEEE, 815-818, 1991.
G.L. Kuhn et al., Thin Silicon Film on Insulating Substrate, J. Electrochem. Soc. Solid State Science and Technology, vol. 120, No. 11, 1563-1566, 1973.
Super Q Etch, Olin Electronic Materials, Olin Corporation, Chandler, AZ (1993).
Box Cell, Toshiba.

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