Etching of semiconductor wafer edges

Details Etching of semiconductor wafer edges Etching of semiconductor wafer edges

1999-03-03

2003-12-09

Kunemund, Robert (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S710000, C438S712000

Reexamination Certificate

active

06660643

ABSTRACT:

FIELD OF THE INVENTION
This invention pertains to plasma etching of semiconductor wafers and more particularly to the etching of the edges of semiconductor wafers.
BACKGROUND OF THE INVENTION
It is a common practice to etch semiconductor wafers to remove selected material from their front and back surfaces and their edges. Thus etching of silicon has been accomplished in various ways, e.g., by chemical (wet acid) etching, plasma etching, reactive ion etching, ion beam etching and chemically assisted mechanical polishing (“CMP”). It also is common to remove material from wafers by grinding.
Silicon solar cells are commonly made from silicon wafers. These wafers are subsequently subjected to various processing steps to produce solar cells, one of those steps involving formation of a photovoltaic p-n junction adjacent to one side of each wafer. The wafers are formed in different ways. They may be sliced from large single crystal Czochralski-grown boules or polycrystalline blocks, e.g., typically by means of a diamond blade saw or a wire saw. Another common method of producing silicon solar cell wafers is to grow hollow polycrystalline bodies by the Edge-Defined Film-Fed Growth (“EFG”) method, and then laser cut those bodies into wafers. Wafers cut from large single crystal boules or polycrystalline blocks are characterized by opposite surfaces that are flat and smooth (sufficiently so that adjacent wafers tend to adhere to one another), while the corresponding surfaces of EFG silicon wafers are uneven. Additionally EFG wafers generally are rectangular in shape, in contrast to those produced from large single crystal boules which commonly have a generally circular configuration (the wafers cut from relatively large cast polycrystalline blocks also are generally rectangular).
EFG semiconductor silicon wafers received from the laser cutting station have edges that have micro-cracks and are tend to be rough due to resolidified material. It has been determined that EFG wafers with micro-cracks at their edges tend to break during subsequent solar cell processing. However, it has been determined that the resistance to fracture of EFG wafers is improved if their edge portions (margins) are etched to give smooth edges that are free of micro-cracks. It should be noted that silicon wafers cut from boules or cast blocks also have edge damage that needs to be removed.
EFG wafers are typically etched using a wet acid etching process, since the other etching techniques mentioned above have not been satisfactory because the etching process throughput rates are too slow and costly. The wet acid etching of EFG wafers serves two purposes: (1) remove edge damage (microcracks) resulting from the laser cutting of the wafers and (2) isotropically remove a thin layer of a film of SiO/SiC that is formed on the back surface of the wafers during the EFG growth process. The etching solution typically is a mixture of nitric and hydrofluoric acids. Using the wet chemical etching process, the EFG-grown wafers are submerged in a bath of the mixed acid solution, with the wafers being kept in the bath long enough to achieve the desired etching.
Although it is effective in improving the resistance to fracture of the EFG wafers, the wet etching process poses other immediate problems. Much floor space is required for the etching equipment and the chemical waste disposal facility. Also the use of the highly corrosive acid mixture poses a continuous hazard. The wet acid etching process also has the disadvantage of producing copious quantities of spent acid which must be neutralized before disposal, and legally disposing of the chemical waste involves substantial cost. Moreover, even with neutralization, an environmental problem remains due to limits on the disposal of the resulting chemical compounds imposed by government authorities.
Prior to this invention it has been deemed desirable to use a plasma etch process to etch the edges of silicon solar cells, after they have been provided with front and back metal contacts, for the purpose of removing sufficient material to assure junction isolation. However, use of a plasma etch process for such purpose is feasible economically only if a plurality of wafers can be etched at the same time and the amount of material required to be removed at each face is relatively small. For effecting junction isolation, the amount of material required to be removed at each edge face typically is in the order of 1 micron. Prior to the present invention it was recognized also that the etch production rate could be increased by stacking a plurality of solar cell wafers together face-to-face in what is commonly called a “coin stack”, and then subjecting that stack to a plasma etch process that is conducted in a plasma etching chamber under a partial vacuum, i.e., at sub-atmospheric pressures. Such a process typically produces what is commonly characterized as a relatively low density plasma which envelops the stack. Edge etching a coin stack of solar cells for junction isolation purposes is disclosed by U.S. Pat. No. 4,158,591, issued Jun. 19, 1979 to J. E. Avery et al. and Charles F. Gay For “Solar Cell Manufacture”. In the Avery et al. process of making solar cells, the stack of solar cells are enveloped by the reactive plasma for a selected period of time sufficient to achieve the desired junction isolation. The Avery et al patent teaches that the plasma etching may be carried out using plasma etching apparatus as described in U.S. Pat. No. 3,795,557.
Using a reactive plasma in the manner taught by Avery et al. to etch the edges of a coin stack of EFG wafers is not satisfactory for several reasons. For one thing, since a plasma produced under a pressure that is less than atmospheric pressure tends to have a relatively low density, the rate of removal of wafer material is comparatively low. That limitation is especially severe in the case of edge etching EFG wafers since the amount of material required to be removed at each edge face to eliminate the micro-cracks is substantially in excess of one (1) micron. EFG silicon wafers currently being used to make solar cells frequently have micro-cracks or roughness due to resolidified material that require as much as 100 microns to be removed from each edge.
A second reason is due to the nature of the EFG wafers. As noted above, the opposite faces of EFG wafers are uneven. More specifically, the surfaces of EFG wafers have undulations that are clearly visible and result in surface flatness deviations of as much as 500 microns. Because of those undulations, and also because of the roughness at the edges caused by resolidified material, when EFG wafers are arranged in a coin stack, they do not adhere to one another and instead there may exist small gaps therebetween into which the reactive plasma can intrude. In this connection it is to be noted that the mean free path of the reactive ions (e.g., fluorine ions) in an etching plasma depends on the density and pressure of the plasma. Under the partial pressures created in the etching chamber, the mean free path of the reactive ions in the plasma surrounding a stack of wafers is such that the ions can travel in the order of millimeters between adjacent EFG wafers, causing uneven etching of the opposites surfaces of each wafer as well as uneven etching of the edge faces of the same wafers.
OBJECT AND SUMMARY OF THE INVENTION
The primary object of this invention is to provide a new method of etching the edges of semiconductor blanks for the purpose of removing damaged edge portions.
Another specific object of the invention is to provide a method of edge-etching semiconductor wafers that are stacked together, with the coin stack being exposed to a reactive plasma in a manner that removes edge damage from the wafers, while limiting the etching substantially to the edges of the wafers.
Another object is to provide a novel method which involves supporting a plurality of semiconductor wafers in a stack and moving that stack so that successive edge portions of the wafers are etched to within predetermined t

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