Semiconductor device manufacturing: process – Chemical etching – Altering etchability of substrate region by compositional or...
Reexamination Certificate
1999-03-29
2002-01-01
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Chemical etching
Altering etchability of substrate region by compositional or...
C438S151000, C438S739000, C216S062000, C216S077000, C216S087000, C216S102000
Reexamination Certificate
active
06335290
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an etching method, a thin film transistor matrix substrate, and its manufacture method.
2. Description of the Related Art
Wet etching and dry etching are known as etching methods. The wet etching uses liquid as the etchant, and most of this method is accompanied with a property of laterally etching (side etching) a region under the mask. The dry etching uses gas as the etchant, and includes isotropic etching which etches also a region under the mask and anisotropic etching which etches only a region exposed outside the mask generally unidirectionally. Various types of etching methods are selectively used in accordance with an etching purpose.
An active matrix liquid crystal display has a switching display has a switching thin film transistor for each pixel and can hold a desired voltage at a pixel electrode. For example, two groups of bus lines crossing each other are formed on a transparent substrate such as a glass plate, and a pixel having a thin film transistor and a pixel electrode is formed at each cross point. One group of bus lines is connected to the gates of thin film transistors to select pixels of each row. The other group of bus lines transfers image information of one row in the form of voltages to the pixels of a selected row.
In order to hold a desired voltage at the pixel electrode for a sufficiently long time, it is desired that the thin film transistor has excellent off-characteristics of sufficiently low leak current during the off-period. In order to change the voltage of the pixel electrode to a desired voltage in a short time during the rewrite period, it is desired that the thin film transistor has excellent on-characteristics of sufficiently low resistance during the on-period.
Various structures of thin film transistors are known. In the following description, a thin film transistor is assumed to have the structure that a semiconductor layer which forms a channel is formed on a glass substrate, and a gate insulating film and a gate electrode are formed on the semiconductor layer.
An island pattern of a semiconductor layer for forming a thin film transistor is formed on an insulating substrate. On this island pattern, a gate insulating film and a gate layer are deposited. A resist pattern is formed on the gate layer to pattern a gate electrode (and a gate wiring pattern). Thereafter, by using the gate electrode as a mask, ions are implanted into the semiconductor layer. With these processes, a single mask can be used both for patterning the gate electrode and implanting ions.
If the gate insulating film is patterned at the same time when the gate electrode is patterned, the semiconductor layer in an outside area of the gate electrode is exposed so that an ion implantation efficiency can be raised.
However, if the gate electrode layer and gate insulating film are patterned in the same shape, a step becomes high. If the wiring area is made narrow, the gate electrode becomes thicker and the step becomes higher. If an interlayer insulating film and other wiring layers are formed over this high step portion, the step coverage becomes poor so that cracks may easily form in the interlayer insulating film and wiring disconnection and interlayer short circuit are likely to occur.
Techniques of forming a low impurity concentration region of a lightly doped drain (LDD) structure through ion implantation using a gate insulating film projecting sideways from the gate electrode have been proposed. For example, an anodic oxide film is formed on the side walls of a gate electrode, the gate insulating film is etched by using the anodic oxide film as a mask, and ions are implanted into the exposed semiconductor layer to form source/drain regions of a high impurity concetration. After the anodic oxide film is removed, ions are again implanted to form low impurity concentration regions under the projecting gate insulating films.
Also in this case, if the gate electrode layer is thick, a high step is formed so that the step coverage of a higher level wiring layer is degraded. Moreover, as the gate insulating film is etched by using the anodic oxide film of the gate electrode as a mask, deposition of conductive materials is likely to be left on the side walls of the gate insulating film. Such conductive deposition is easy to grow in a needle shape during a later heat treatment or the like so that the step coverage of a higher level wiring layer is degraded.
In order to improve a step coverage of a higher level layer of a lamination structure, it is desired to moderate a step. However, techniques of moderating a step of a thin film transistor formed on an insulating substrate such as a glass substrate have not been sufficiently developed.
In order to reduce leak current during the off-period and to suppress damages of a gate insulating film to be caused by hot carriers during the on-period in a thin film transistor using polycrystalline semiconductor, adopting an LDD structure or an offset structure is desired. However, these structures increase the number of processes. As the number of masks increases, the manufacture cost of a thin film transistor rises.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an etching method capable of moderating a step.
It is another object of the present invention to provide a method of manufacturing a thin film transistor matrix substrate excellent in step coverage.
It is another object of the present invention to provide a thin film transistor matrix substrate excellent in step coverage and low in a manufacture cost.
According to one aspect of the present invention, there is provided a method of etching an Al or Al alloy layer, comprising the steps of: (a) forming an Al or Al alloy layer on an underlying surface; (b) processing a surface of the Al or Al alloy layer with tetramethylammonium hydroxide (TMAH); (c) forming a resist pattern on the surface of the Al or Al alloy layer processed with TMAH; and (d) by using the resist pattern as an etching mask, wet-etching the Al or Al alloy layer.
As the Al or Al alloy layer processed with TMAH (tetramethylammonium hydroxide) is wet-etched, side walls having a normal or pyramid-like taper are formed. The side walls of a normal taper improve the step coverage of the higher level layer.
According to another aspect of the present invention, there is provided a thin film transistor matrix substrate comprising: an insulating substrate having a flat surface; a plurality of island patterns made of semiconductor and formed on the flat surface of the insulating substrate; a gate insulating film formed traversing a central area, in plan view, of each of the plurality of island patterns; and a gate layer formed on a central surface area of the gate insulating film and exposing a wing of the gate insulating film on both sides thereof, the gate layer having side walls of a normal taper slanted relative to a normal to the flat surface of the insulating substrate and an upper surface generally perpendicular to the normal, and serving as both gate electrode and a gate wiring pattern.
According to another aspect of the present invention, there is provided a method of manufacturing a thin film transistor matrix comprising the steps of: (a) forming a semiconductor layer on an insulating substrate; (b) forming a gate insulating film on the semiconductor layer; (c) forming a gate layer made of Al or Al alloy on the gate insulating film; (d) processing a surface of the gate layer with TMAH; (e) forming a resist pattern on the surface of the gate layer processed with TMAH; (f) by using the resist pattern as an etching mask, wet-etching the gate layer while the gate layer is formed with side walls of a normal taper; and (g) anisotropically dry-etching the gate insulating film by using the resist pattern as an etching mask.
The side walls of a normal taper of the gate layer improve the step coverage of an interlayer insulating film, a wiring layer and the like formed on the gate layer.
By covering the surfac
Fujitsu Limited
Greer Burns & Crain Ltd.
Niebling John F.
Simkovic Viktor
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